DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
5. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21354/DS21554 is configured via a set of 10 control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the device has been
initialized, the control registers need only to be accessed when there is a change in the system
configuration. There are two receive control registers (RCR1 and RCR2), two transmit control registers
(TCR1 and TCR2), and six common control registers (CCR1 to CCR6). Each of the 10 registers is
described in this section.
There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed
to a one, indicating that an E1 SCT is present. The next three MSBs are used to indicate which E1 device
is present—DS2154, DS21354, or DS21554. The T1 pin-for-pin compatible SCTs have a logic zero in
the MSB position with the following three MSBs indicating which T1 SCT is present—DS2152,
DS21352, or DS21552. Table 5-1 represents the possible variations of these bits and the associated SCT.
Table 5-1. Device ID Bit Map
SCT
T1/E1
BIT 6
BIT 5
BIT 4
DS2152
DS21352
DS21552
DS2154
DS21354
DS21554
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
The lower four bits of the IDR are used to display the die revision of the chip. The test registers at
addresses 09, 15, 19, and AC hex are used by the factory in testing the DS21354/DS21554. On power-up,
the test registers should be set to 00h in order for the DS21354/DS21554 to operate properly. Certain bits
of TEST3 are used to select monitor mode functions. Please see Section 15.5 for further details.
5.1. Power-Up Sequence
On power-up, after the supplies are stable the DS21354/DS21554 should be configured for operation by
writing to all the internal registers (this includes setting the test registers to 00h) since the contents of the
internal registers cannot be predicted on power-up. The LIRST (CCR5.7) should be toggled from zero to
one to reset the line-interface circuitry (it will take the device about 40ms to recover from the LIRST bit
being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bits (CCR6.0 and
CCR6.1) should be toggled from a zero to a one (this step can be skipped if the elastic stores are
disabled).
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