DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-12. Transmit System Side AC Timing
t
SP
t
t
SL
SH
t
t
F
R
TSYSCLK
TSER
t
SU
t
t
D3
HD
TCHCLK / CO
TCHBLK
t
D3
t
HD
t
SU
TSSYNC
t
WC
t
SC
CI
Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
Figure 20-13. Transmit Line Interface Side AC Timing
TCLKO
TPOSO, TNEGO
t
DD
t
LP
t
t
LL
LH
t
t
F
R
TCLKI
t
SU
TPOSI, TNEGI
t
HD
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