DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
20.3. Receive-Side AC Characteristics
AC CHARACTERISTICS—RECEIVE SIDE
(VDD = 3.3V M5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V M5%, TA = 0°C to +70°C for DS21554L;
VDD = 3.3V M5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V M5%, TA = -40LC to +85LC for DS21554LN.)
(See Figure 20-8 to Figure 20-10.)
PARAMETER
RCLKO Period
SYMBOL MIN
TYP
488
MAX UNITS NOTES
tLP
ns
tLH
200
244
ns
1
RCLKO Pulse Width
tLL
tLH
tLL
tCP
tCH
200
150
150
244
244
244
488
ns
ns
ns
ns
ns
1
2
2
RCLKO Pulse Width
RCLKI Period
75
RCLKI Pulse Width
tCL
tSP
tSP
tSP
tSP
tSH
tSL
tSU
tPW
tSU
tHD
75
100
100
100
100
50
50
20
50
20
20
ns
ns
ns
ns
ns
ns
648
488
244
122
3
4
5
6
RSYSCLK Period
RSYSCLK Pulse Width
ns
ns
ns
ns
ns
RSYNC Setup to RSYSCLK Falling
RSYNC Pulse Width
tSH –5
RPOSI/RNEGI Setup to RCLKI Falling
RPOSI/RNEGI Hold From RCLKI
Falling
RSYSCLK/RCLKI Rise and Fall Times
Delay RCLKO to RPOSO, RNEGO
Valid
tR, tF
tDD
25
50
ns
ns
Delay RCLK to RSER, RDATA, RSIG,
RLINK Valid
tD1
tD2
50
50
ns
ns
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
Delay RSYSCLK to RSER, RSIG Valid
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC, CO
CI Setup to RSYSCLK Rising
CI Pulse Width
tD3
tD4
50
50
ns
ns
tSC
20
50
ns
ns
tWC
Note 1: Jitter attenuator enabled in the receive path.
Note 2: Jitter attenuator disabled or enabled in the transmit path.
Note 3: RSYSCLK = 1.544MHz.
Note 4: RSYSCLK = 2.048MHz.
Note 5: RSYSCLK = 4.096MHz.
Note 6: RSYSCLK = 8.192MHz.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
