DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Figure 20-11. Transmit-Side AC Timing
t
CP
t
t
CL
CH
t
t
F
R
TCLK
TESO
t
D1
t
SU
TSER / TSIG /
TDATA
t
t
HD
D2
TCHCLK
TCHBLK
t
D2
t
D2
1
TSYNC
t
HD
t
SU
2
TSYNC
t
D2
5
TLCLK
t
HD
TLINK
Notes:
t
SU
1. TSYNC is in the output mode (TCR1.0 = 1).
2. TSYNC is in the input mode (TCR1.0 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between
TLCLK/TLINK and TSYNC is implied.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
