DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
20.4. Transmit AC Characteristics
AC CHARACTERISTICS—TRANSMIT SIDE
(VDD = 3.3V M5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V M5%, TA = 0°C to +70°C for DS21554L;
VDD = 3.3V M5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V M5%, TA = -40LC to +85LC for DS21554LN.)
(See Figure 20-11 to Figure 20-13.)
PARAMETER
TCLK Period
SYMBOL
tCP
MIN
TYP
MAX UNITS NOTES
488
ns
ns
ns
ns
ns
ns
tCH
75
75
TCLK Pulse Width
TCLKI Period
tCL
tLP
488
tLH
75
75
TCLKI Pulse Width
tLL
tSP
100
100
100
100
50
648
448
244
122
ns
ns
ns
ns
ns
ns
1
2
3
4
tSP
TSYSCLK Period
tSP
tSP
tSH
TSYSCLK Pulse Width
tSL
50
tCH –5
or
TSYNC or TSSYNC Setup to TCLK
or TSYSCLK Falling
tSU
tPW
tSU
20
50
20
ns
ns
ns
tSH –5
TSYNC or TSSYNC Pulse Width
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Setup to TCLK,
TSYSCLK, TCLKI Falling
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Hold from TCLK,
TSYSCLK, TCLKI Falling
TCLK, TCLKI, or TSYSCLK Rise
and Fall Times
tHD
20
ns
ns
tR, tF
25
Delay TCLKO to TPOSO, TNEGO
Valid
tDD
tD1
tD2
50
50
50
ns
ns
ns
Delay TCLK to TESO Valid
Delay TCLK to TCHBLK, TCHCLK,
TSYNC, TLCLK
Delay TSYSCLK to TCHCLK,
TCHBLK, CO
tD3
75
ns
CI Setup to TSYSCLK Rising
CI Pulse Width
tSC
20
50
ns
ns
tWC
Note 1: TSYSCLK = 1.544MHz.
Note 2: TSYSCLK = 2.048MHz.
Note 3: TSYSCLK = 4.096MHz.
Note 4: TSYSCLK = 8.192MHz.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
