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DS2154LNA2+ 参数 Datasheet PDF下载

DS2154LNA2+图片预览
型号: DS2154LNA2+
PDF下载: 下载PDF文件 查看货源
内容描述: [Framer, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-100]
分类和应用: PC电信电信集成电路
文件页数/大小: 124 页 / 982 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers  
20. AC TIMING PARAMETERS AND DIAGRAMS  
20.1. Multiplexed Bus AC Characteristics  
AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (MUX = 1)  
(VDD = 3.3V M5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V M5%, TA = 0°C to +70°C for DS21554L;  
VDD = 3.3V M5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V M5%, TA = -40LC to +85LC for DS21554LN.)  
(See Figure 20-1 to Figure 20-3.)  
PARAMETER  
SYMBOL MIN TYP MAX UNITS NOTES  
tCYC  
PWEL  
PWEH  
tR, tF  
tRWH  
200  
100  
100  
ns  
ns  
ns  
ns  
ns  
ns  
Cycle Time  
Pulse Width, DS Low or RD High  
Pulse Width, DS High or RD Low  
Input Rise/Fall Yimes  
20  
50  
10  
50  
R/W Hold Time  
tRWS  
R/W Setup Time before DS High  
CS Setup Time before DS, WR, or RD  
tCS  
20  
ns  
Active  
tCH  
tDHR  
tDHW  
tASL  
tAHL  
0
10  
0
15  
10  
ns  
ns  
ns  
ns  
ns  
CS Hold Time  
Read Data Hold Time  
Write Data Hold Time  
Muxed Address Valid to AS or ALE Fall  
Muxed Address Hold Time  
Delay time DS, WR, or RD to AS or ALE  
tASD  
20  
ns  
Rise  
PWASH  
tASED  
tDDR  
30  
10  
20  
50  
ns  
ns  
ns  
ns  
Pulse Width AS or ALE High  
Delay time, AS or ALE to DS, WR, or RD  
Output Data Delay Time from DS or RD  
Data Setup Time  
80  
tDSW  
112 of 124  
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