71M6543F/H and 71M6543G/GH Data Sheet
OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse
modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured
as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).
V3P3
VARPULSE
WPULSE
DIO2
Internal
3
2
1
OPT_TX
from
OPT_TX UART
A
MOD
B
0
OPT_TXINV
EN DUTY
2
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
OPT_TXMOD = 1,
OPT_FDC = 2 (25%)
OPT_TXMOD = 0
A
B
A
B
1/38kHz
Figure 14: Optical Interface
Bit Banged Optical UART (Third UART)
As shown in Figure 15, the 71M6543 can also be configured to drive the optical UART with a DIO signal
in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port is
driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used when
the two dedicated UARTs must be connected to high speed clients and a slower optical UART is
permissible.
Internal
SEG55
DIO55
1
0
1
0
SEGDIO55/
OPT_RX
UART1_RX
SEG51 LCD_MAP[55]
OPT_RXDIS
V3P3
VARPULSE
WPULSE
DIO51
3
1
1
0
SEGDIO51/
OPT_TX
2
0
0
1
UART1_TX
DIO5
MOD
LCD_MAP[51]
A
B
EN
DUTY
OPT_TXE[1:0]
SEG5
OPT_TXMOD
OPT_FDC
OPT_TXINV
2
0
1
0
SEGDIO5/TX2
1
LCD_MAP[5]
OPT_BB
OPT_TXMOD=1,
OPT_TXMOD=0
OPT_FDC=2 (25%)
A
B
1/38kHz
Figure 15: Optical Interface (UART1)
2.5.10 Digital I/O and LCD Segment Drivers
2.5.10.1 General Information
The 71M6543 combines most DIO pins with LCD segment drivers. Each SEG/DIO pin can be configured
as a DIO pin or as a segment driver pin (SEG).
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
58
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