71M6543F/H and 71M6543G/GH Data Sheet
MISSION
MISSION
V3P3SYS
V3P3SYS
VBAT
LCD/SLEEP
LCD/SLEEP
BROWNOUT
BROWNOUT
VBAT
V3P3D
V3P3D
HIGH
HIGH
HIGH-Z
LOW
HIGH-Z
DIO
DIO
LOW
GNDD
GNDD
Not recommended
Recommended
Figure 16: Connecting an External Load to DIO Pins
2.5.10.2 Combined DIO and SEG Pins
A total of 51 combined DIO/LCD pins are available. These pins can be categorized as follows:
39 combined DIO/LCD segment pins:
o
o
o
o
SEGDIO4…SEGDIO25 (22 pins)
SEGDIO28…SEGDIO35 (8 pins)
SEGDIO40…SEGDIO45 (6 pins)
SEGDIO52…SEGDIO54 (3 pins)
12 combined DIO/LCD segment pins shared with other functions:
o
o
o
o
o
SEGDIO0/WPULSE, SEGDIO1/VPULSE (2 pins)
SEGDIO2/SDCK, SEGDIO3/SDATA (2 pins)
SEGDIO26/COM5, SEGDIO27/COM4 (2 pins)
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
Additionally, 5 LCD segment (SEG) pins are available. These pins can be categorized as follows:
o
3 SEG pins combined with the ICE interface (SEG48/E_RXTX, SEG49/E_TCLK,
SEG50/E_RST)
o
2 SEG pins combined with the test multiplexer outputs (SEG46/TMUX2OUT,
SEG47/TMUXOUT)
Thus, a total of 51 DIO pins are available with minimum LCD configuration, and a total of 56 LCD pins are
available with minimum DIO configuration.
Table 48: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15
SEGDIO
Pin #
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
45 44 43 42 41 39 38 37 36 35
34
33 32 31 30 29
0
0
0
4
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Configuration:
0 = DIO, 1 = LCD
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_MAP[15:8] (I/O RAM 0x240A)
10 11 12 13 14 15
1
2
3
4
5
6
7
8
9
SEG Data Register
DIO Data Register
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
7
P0 (SFR80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
5
6
7
4
5
6
7
4
5
6
7
4
5
6
Direction Register:
0 = input, 1 = output
P0 (SFR 0x80)
P1 (SFR 0x90)
P2 (SFR 0xA0)
P3 (SFR 0xB0)
60
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