71M6543F/H and 71M6543G/GH Data Sheet
Table 42: Clock System Summary
Fixed Frequency or Range
PLL_FAST=1 PLL_FAST=0 Controlled by
32.768 kHz
Derived
From
Clock
Function
OSC
Crystal
–
Crystal clock
Master clock
CE clock
19.660800 MHz
(600*CK32)
6.291456 MHz
(192*CK32)
PLL_FAST
–
MCK
Crystal/PLL
MCK
CKCE
CKADC
4.9152 MHz
1.5728 MHz
1.572864 MHz,
0.786432 MHz
4.9152 MHz,
2.4576 MHz
ADC_DIV
MCK
ADC clock
4.9152 MHz … 1.572864 MHz…
MPU_DIV[2:0]
MPU_DIV[2:0]
CKMPU
CKICE
MCK
MCK
MPU clock
ICE clock
307.2 kHz
9.8304 MHz…
614.4 kHz
98.304 kHz
3.145728 MHz …
196.608 kHz
Optical
UART
Modulation
CKOPTMOD MCK
CK32 MCK
38.40 kHz
38.6 kHz
–
–
32.768 kHz
32 kHz clock
2.5.4 Real-Time Clock (RTC)
2.5.4.1 RTC General Description
The RTC is driven directly by the crystal oscillator and is powered by either the V3P3SYS pin or the
VBAT_RTC pin, depending on the V3OK internal bit. The RTC consists of a counter chain and output
registers. The counter chain consists of registers for seconds, minutes, hours, day of week, day of month,
month, and year. The chain registers are supported by a shadow register that facilitates read and write
operations.
Table 43 shows the I/O RAM registers for accessing the RTC.
2.5.4.2 Accessing the RTC
Two bits, RTC_RD (I/O RAM 0x2890[6]) and RTC_WR (I/O RAM 0x2890[7]), control the behavior of the
shadow register.
When RTC_RD is low, the shadow register is updated by the RTC after each two milliseconds. When
RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable
to be read by the MPU. Thus, when the MPU wishes to read the RTC, it freezes the shadow register by
setting the RTC_RD bit, reads the shadow register, and then lowers the RTC_RD bit to let updates to the
shadow register resume. Since the RTC clock is only 500 Hz, there may be a delay of approximately
2 ms from when the RTC_RD bit is lowered until the shadow register receives its first update. Reads to
RTC_RD continues to return a one until the first shadow update occurs.
When RTC_WR is high, the update of the shadow register is also inhibited. During this time, the MPU may
overwrite the contents of the shadow register. When RTC_WR is lowered, the shadow register is written into
the RTC counter on the next 500Hz RTC clock. A ‘change’ bit is included for each word in the shadow
register to ensure that only programmed words are updated when the MPU writes a zero to RTC_WR.
Reads of RTC_WR returns one until the counter has actually been updated by the register.
The sub-second register of the RTC, RTC_SBSC (I/O RAM 0x2892), can be read by the MPU after the one
second interrupt and before reaching the next one second boundary. RTC_SBSC contains the count since
the last full second, in 1/128 second nominal clock periods, until the next one-second boundary. When the
RST_SUBSEC bit is written, the SUBSEC counter is restarted, counting from 0 to 127. Reading and resetting
the sub-second counter can be used as part of an algorithm to accurately set the RTC.
The RTC is capable of processing leap years. Each counter has its own output register. The RTC chain
registers are not be affected by the reset pin, watchdog timer resets, or by transitions between the battery
modes and mission mode.
v1.2
© 2008–2011 Teridian Semiconductor Corporation
51
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
