71M6543F/H and 71M6543G/GH Data Sheet
Table 43: RTC Control Registers
Location Rst Wk Dir Description
Name
RTCA_ADJ[6:0]
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
2504[6:0] 40
--
4
0
0
0
R/W Register for analog RTC frequency adjustment.
289B[2:0]
289C[7:0]
289D[7:2]
289D[1:0]
4
0
0
0
R/W
Registers for digital RTC adjustment.
0x0FFBF ≤ RTC_P ≤ 0x10040
RTC_Q[1:0]
R/W Register for digital RTC adjustment.
Freezes the RTC shadow register so it is suitable for
MPU reads. When RTC_RD is read, it returns the
status of the shadow register: 0 = up to date, 1 =
frozen.
RTC_RD
2890[6]
0
0
R/W
Writing 0 to RTC_RD bit to enable shadow register
update, and writing 1 to RTC_RD to disable update
Freezes the RTC shadow register so it is suitable for
MPU write operations. When RTC_WR is cleared, the
contents of the shadow register are written to the RTC
counter on the next RTC clock (~1 kHz). When
RTC_WR is read, it returns 1 as long as RTC_WR is
set, and continues to return one until the RTC counter
is updated.
Writing 0 to RTC_WR bit to enable copying the shadow
register contents to RTC counter, and writing 1 to
RTC_WR to disable copying
RTC_WR
2890[7]
0
0
0
0
R/W
Indicates that a count error has occurred in the RTC
R/W and that the time is not trustworthy. This bit can be
cleared by writing a 0.
RTC_FAIL
2890[4]
Time remaining since the last 1 second boundary.
LSB = 1/128 second.
RTC_SBSC[7:0]
2892[7:0]
R
2.5.4.3 RTC Rate Control
The 71M6543 has two rate adjustment mechanisms:
•
•
The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0], that trims the crystal load capacitance.
The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is processed in the RTC.
Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0] to 0x7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable
capacitance is approximately:
RTCA_ ADJ
CADJ
=
⋅16.5pF
128
The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the
external crystal capacitors (see CXS and CXS in Table 89). The adjustment may occur at any time, and the
resulting clock frequency should be measured over a one-second interval.
The second rate adjustment is digital, and can be used to adjust the clock rate up to ±988ppm, with a
resolution of 3.8 ppm. The rate adjustment is implemented starting at the next second-boundary
following the adjustment. Since the LSB (define first) results in an adjustment every four seconds, the
frequency should be measured over an interval that is a multiple of four seconds.
The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and
RTC_Q, are done through the shadow register described above. The new values are loaded into the
counters when RTC_WR (I/O RAM 0x2890[7]) is lowered.
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