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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
2.5  
On-Chip Resources  
2.5.1 Physical Memory  
2.5.1.1 Flash Memory  
The device includes 64 KB (71M6543F/H) or 128 KB (71M6543G/GH) of on-chip flash memory. The  
flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and  
I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective  
locations.  
Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must  
begin on a 1-KB boundary of the flash address space. The CE_LCTN[6/5:0] (I/O RAM 0x2109[5:0]) field  
on the 71M6543F/H and the CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) field on the 71M6543G/GH define  
which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at  
1024*CE_LCTN[6/5:0] on the 71M6543F/H and at 1024*CE_LCTN[6:0] on the 71M6543G/GH.  
Flash memory can be accessed by the MPU, the CE, and by the SPI interface (R/W).  
Table 39: Flash Memory Access  
Access  
Access by  
Condition  
Type  
R/W/E  
R
MPU  
CE  
W/E only if CE is disabled.  
SPI  
R/W/E  
Access only when SFM is invoked (MPU halted).  
Flash Write Procedures  
If the FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) key is correctly programmed, the MPU may write to the  
flash memory. This is one of the non-volatile storage options available to the user in addition to external  
EEPROM.  
The flash program write enable bit, FLSH_PSTWR (SFR 0xB2[0]), differentiates 80515 data store instructions  
(MOVX@DPTR,A) between Flash and XRAM writes. This bit is automatically cleared by hardware after  
each byte write operation. Write operations to this bit are inhibited when interrupts are enabled.  
If the CE is enabled (CE_E = 1, I/O RAM 0x2106[0]), flash write operations must not be attempted unless  
FLSH_PSTWR is set. This bit enables the “posted flash write” capability. FLSH_PSTWR has no effect when  
CE_E = 0). When CE_E = 1, however, FLSH_PSTWR delays a flash write until the time interval between  
the CE code passes. During this delay time, the FLSH_PEND (SFR 0xB2[3]) bit is high, and the MPU  
continues to execute commands. When the CE code pass ends (CE_BUSY falls), the FLSH_PEND bit  
falls and the write operation occurs. The MPU can query the FLSH_PEND bit to determine when the  
write operation has been completed. While FLSH_PEND = 1, further flash write requests are ignored.  
Updating Individual Bytes in Flash Memory  
The original state of a flash byte is 0xFF (all bits are 1). Once a value other than 0xFF is written to a flash  
memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells  
cannot be erased individually, the page has to be first copied to RAM, followed by a page erase. After  
this, the page can be updated in RAM and then written back to the flash memory.  
Flash Erase Procedures  
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.  
These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.  
The mass erase sequence is:  
Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).  
Write the pattern 0xAA to the FLSH_ERASE (SFR 0x94) register.  
The mass erase cycle can only be initiated when the ICE port is enabled.  
v1.2  
© 2008–2011 Teridian Semiconductor Corporation  
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