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71M6543H 参数 Datasheet PDF下载

71M6543H图片预览
型号: 71M6543H
PDF下载: 下载PDF文件 查看货源
内容描述: 可选增益1或8的一个电流电能表计量芯片的补偿 [Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation]
分类和应用:
文件页数/大小: 157 页 / 2164 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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71M6543F/H and 71M6543G/GH Data Sheet  
Bit  
Symbol  
TB80  
Function  
S0CON[3]  
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,  
depending on the function it performs (parity check, multiprocessor  
communication etc.)  
In Modes 2 and 3 it is the 9th data bit received. In Mode 1, SM20 is 0, RB80 is the  
S0CON[2]  
S0CON[1]  
S0CON[0]  
RB80  
TI0  
stop bit. In mode 0, this bit is not used. Must be cleared by software.  
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must  
be cleared by software (see Caution above).  
RI0  
Receive interrupt flag; set by hardware after completion of a serial reception. Must  
be cleared by software (see Caution above).  
Table 20: The S1CON (UART1) Register (SFR 0x9B)  
Bit  
Symbol  
Function  
S1CON[7]  
SM  
Sets the baud rate and mode for UART1.  
Mode  
Description  
9-bit UART  
8-bit UART  
Baud Rate  
variable  
SM  
0
A
B
1
variable  
S1CON[5]  
S1CON[4]  
S1CON[3]  
SM21  
REN1  
TB81  
Enables the inter-processor communication feature.  
If set, enables serial reception. Cleared by software to disable reception.  
The 9th transmitted data bit in Mode A. Set or cleared by the MPU, depending  
on the function it performs (parity check, multiprocessor communication etc.)  
In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0, RB81 is  
S1CON[2]  
S1CON[1]  
S1CON[0]  
RB81  
TI1  
the stop bit. Must be cleared by software  
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must  
be cleared by software (see Caution above).  
RI1  
Receive interrupt flag, set by hardware after completion of a serial reception. Must  
be cleared by software (see Caution above).  
Table 21: PCON Register Bit Description (SFR 0x87)  
Bit  
Symbol  
SMOD  
Function  
PCON[7]  
The SMOD bit doubles the baud rate when set  
2.4.7 Timers and Counters  
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured  
for counter or timer operations.  
In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods of  
the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the  
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see  
2.5.10 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate  
is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper  
recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle.  
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 22 and Table 23. The  
TMOD (SFR 0x89) register, shown in  
Table 24, is used to select the appropriate mode. The timer/counter operation is controlled by the TCON  
(SFR 0x88) register, which is shown in Table 25. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON  
register start their associated timers when set.  
38  
© 2008–2011 Teridian Semiconductor Corporation  
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