MCP795WXX/MCP795BXX
FIGURE 9-5:
READ STATUS REGISTER TIMING SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
0
0
0
0
0
1
0
1
Data from STATUS Register
High-Impedance
SO
7
6
5
4
3
2
1
0
* Data should be able to continuously be read from the STATUS register without toggling CS, for updating of
the WIP and WEL bits.
DS22280A-page 34
Preliminary
2011 Microchip Technology Inc.