MCP795WXX/MCP795BXX
• The second set of registers, located at 0x1Ch
through 0x1Fh, are loaded at the time when VCC
is restored and the RTCC switches to VCC.
9.1.7
POWER-FAIL TIME-STAMP
The MCP795XXX family of RTCC devices feature a
power-fail time-stamp feature. This feature will save the
time at which VCC crosses the VTRIP voltage and is
shown in Figure 9-4. To use this feature, a VBAT supply
must be present and the oscillator must also be run-
ning. There are two separate sets of registers that are
used to record this information:
The power-fail time-stamp registers are cleared when
the VBAT bit is cleared in software.
Note:
It is strongly recommended that the time-
saver function only be used when the
oscillator is running. This will ensure accu-
rate functionality
• The first set located at 0x18h through 0x1Bh are
loaded at the time when VCC falls below VTRIP
and the RTCC operates on the VBAT. The VBAT
(register 0x03h bit 4) bit is also set at this time.
FIGURE 9-4:
POWER-FAIL GRAPH
VCC
VTRIP(max)
VTRIP(min)
Power-Down
Time-Stamp
Power-Up
Time-Stamp
via the WREN or WRDI commands, regardless of the
state of write protection on the STATUS register. This
bit is read-only.
9.1.8
READ STATUS REGISTER
(SRREAD)
The Read Status Register (SRREAD) instruction pro-
vides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. The STATUS register is formatted as follows:
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSRinstruction. These
bits are nonvolatile.
7
—
X
6
5
4
3
2
1
0
See Figure 9-5 for the RDSR timing sequence.
—
X
—
X
—
X
R/W R/W
R
R
BP1 BP0 WEL WIP
*
Note:
Once a Write Status Register is initiated
and a Read Status Register is attempted
the new values for the nonvolatile bits will
be read regardless of whether the values
have been actually programmed into the
device. (i.e., The values are moved to the
latches prior to the write operation).
The Write-In-Process (WIP) bit indicates whether the
MCP795XXX is busy with a nonvolatile memory write
operation. When set to a ‘1’, a write is in progress,
when set to a ‘0’, no write is in progress. This bit is
read-only.
The Write Enable Latch (WEL) bit indicates the sta-
tus of the write enable latch. When set to a ‘1’, the
latch allows writes to the nonvolatile memory, when
set to a ‘0’, the latch prohibits writes to the nonvolatile
memory. The state of this bit can always be updated
2011 Microchip Technology Inc.
Preliminary
DS22280A-page 33
MAS [ MICRO ANALOG SYSTEMS ]
