DA9560.001
20 January, 2005
SPI BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical values at TA = +27°C,
Parameter
Pin
Conditions
Min
Nom
Mauxnless otherwise noted
Unit
Name
Input Low voltage
Input High voltage
Input Impedance
SDI,
SCLK
tbd
IOVDD
IOVDD
pF
tbd
tbd
tbd
Input Leakage Current
0 V
tbd
Tbd
Tbd
µA
< Input < IOVDD
Input Setup Time before
clock rising edge
SDI,
XCS
ns
ns
V
Input Hold Time after clock
SDI,
falling edge
XCS
Output Low Voltage
Output High Voltage
SDO
SDO
ILOAD = 0.5 mA,
IOVDD = 1.8 V
tbd
ILOAD = -0.5 mA,
tbd
V
IOVDD = 1.8 V
Clock Frequency, read
access
SCLK, CLOAD = 20 pF,
tbd
tbd
tbd
tbd
MHz
SDI,
IOVDD = 3.3 V
SDO
Clock Frequency, read
access
SCLK, CLOAD = 20 pF,
MHz
SDI,
IOVDD = 1.8 V
SDO
Clock Frequency, write
access
SCLK, CLOAD = 20 pF,
tbd
tbd
tbd
tbd
MHz
MHz
SDI IOVDD = 3.3 V
Clock Frequency, write
SCLK, CLOAD = 20 pF,
SDI IOVDD = 1.8 V
access
I2S BUS TIMING
LSVDD = VBAT = 3.6V, EPVDD = HPVDD = VLDO = 2.86V (LDO-mode), -40°C ≤ TA ≤ +85°C, typical values at TA = +27°C,
unless otherwise noted
Parameter
Pin
Conditions
Min
Nom
Max
Unit
Name
Input Low Voltage
Input High voltage
Input Impedance
DAI,
CLI,
WSI
tbd
IOVDD
IOVDD
pF
µA
ns
tbd
tbd
tbd
Input Leakage Current
0 V < Input < IOVDD
tbd
tbd
Input Setup Time before
DAI,
WSI
clock rising edge
Input Hold Time after clock
falling edge
DAI,
tbd
ns
WSI
Clock Frequency (Note 1)
CLI,
DAI
tbd
MHz
Note 1: I2S clock (CLI) frequency ratio will affect to DAC sampling in oversampling mode. See Control Register
description (p. 18)
23 (25)
MAS [ MICRO ANALOG SYSTEMS ]
