DA9560.001
20 January, 2005
◆ Register Description
Name
Sub-
Direction Default
Function
Address
after
Reset
0x00
Write
Write
0x00
X
Reset Register
Reset
0xXX
Writing to the register clears all internal
registers to their default reset values.
Register value cannot be read.
0x01
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
Ignored, if Standby or Zero Power Mode
Block Control Register
PDAC
PAIN
PAUX
PL
PE
PRH
0x01[7]
0x01[6]
0x01[5]
0x01[4]
0x01[3]
0x01[2]
0
0
0
0
0
0
DAC power: 1 = on, 0 = off
AIN power: 1 = on, 0 = off
AUX power: 1 = on, 0 = off
Loudspeaker driver power: 1 = on, 0 = off
Earpiece driver power: 1 = on, 0 = off
Right Headphone driver power:
1 = on, 0 = off
PLH
PCH
0x01[1]
0x01[0]
R/W
R/W
0
0
Left Headphone driver power:
1 = on, 0 = off
Common Headphone driver power:
1 = on, 0 = off
0x02
R/W
-
R/W
0x00
Mode Control Register
-
BYPLDO
0x02[7:5]
0x02[4]
-
0
Unused
Bypass LDO (in non-LDO mode only):
1 = on (bypass LDO with 100 ohm on-chip
resistor connected between VLDO and
VBAT)
0 = off (LDO not bypassed, so on-chip
resistor not connected between VLDO and
VBAT)
SNLDOM
SMM
0x02[3]
0x02[2]
R/W
R/W
0
0
Select Non-LDO mode: 1 = on, 0 = off
LDO is always disabled at Zero Power
Mode
Select Stereo/Mono mode:
1 = Mono, 0 = Stereo
In Mono Mode AUXL and AUXR are
combined together and only left channel
DAC signal is used.
19 (25)
MAS [ MICRO ANALOG SYSTEMS ]
