MV78100
Hardware Specifications
9.6.8
Two-Wire Serial Interface (TWSI) AC Timing
9.6.8.1
TWSI AC Timing Table
Table 45: TWSI Master AC Timing Table
Description
SCK clock frequency
Symbol
fCK
tLOW
tHIGH
tSU
Min
Max
Units
kHz
tCK
tCK
ns
Notes
See note 1
1
2
SCK minimum low level w idth
0.47
0.40
250.0
0.0
-
-
SCK minimum high level w idth
-
2
SDA input setup time relative to SCK rising edge
SDA input hold time relative to SCK falling edge
SDA and SCK rise time
-
-
-
tHD
ns
-
tr
1000.0
300.0
0.4
ns
2, 3
2, 3
2
SDA and SCK fall time
tf
-
ns
SDA output delay relative to SCK falling edge
tOV
0.0
tCK
Notes :
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
Table 46: TWSI Slave AC Timing Table
100 kHz (Max)
Description
SCK minimum low level w idth
Symbol
tLOW
tHIGH
tSU
Min
4.7
4.0
250.0
0.0
-
Max
Units
us
Notes
-
1
1
SCK minimum high level w idth
-
us
SDA input setup time relative to SCK rising edge
SDA input hold time relative to SCK falling edge
SDA and SCK rise time
-
-
ns
-
tHD
ns
-
tr
1000.0
300.0
4.0
ns
1, 2
1, 2
1
SDA and SCK fall time
tf
-
ns
SDA output delay relative to SCK falling edge
tOV
0.0
us
Notes :
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
MV-S104552-U0 Rev. D
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Page 94
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
