MV78100
Hardware Specifications
9.6.9.2
Device Bus Interface Test Circuit
Figure 32: Device Bus Interface Test Circuit
Test Point
CL
9.6.9.3
Device Bus Interface AC Timing Diagram
Figure 33: Device Bus Interface Output Delay AC Timing Diagram
Vih(min)
CLOCK
DATA
Vil(max)
Vih(min)
Vil(max)
TOV(min)
TOV(max)
Vih(min)
Vil(max)
ALE
Vih(min)
Vil(max)
AD Bus
TAOAB
TAOAA
MV-S104552-U0 Rev. D
Page 98
Copyright © 2008 Marvell
December 6, 2008, Preliminary
Document Classification: Proprietary Information