Electrical Specifications
9.6.9
Device Bus Interface AC Timing
9.6.9.1
Device Bus Interface AC Timing Table
Table 47: Device Bus Interface AC Timing Table (when using TCLK_OUT as the reference clock)
Description
Symbol
tSU
Min
3.0
1.0
0.8
7.5
3.5
Max
Units
ns
Notes
Data/READYn input setup relative to clock rising edge
Data/READYn input hold relative to clock rising edge
Address/Data output delay relative to clock rising edge
Address output valid before ALEsignal falling edge
Address output valid after ALEsignal falling edge
-
-
-
-
tHD
ns
tOV
3.5
-
ns
1
tAOAB
tAOAA
ns
1 , 2
1 , 2
-
ns
Notes :
General comment: All timing values are for interfacing synchronous devices.
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
1. For all signals, the load is CL = 10 pF.
2. The AD bus is normally loaded w ith high capacitance. Make sure to w ork according to HW design guidelines
or simulations in order to meet the latch AC timing requirements.
Table 48: Device Bus Interface AC Timing Table (when using TCLK_IN as the reference clock)
Description
Symbol
tSU
Min
1.5
0.5
1.5
5.2
2.8
Max
Units
ns
Notes
Data/READYn input setup relative to clock rising edge
Data/READYn input hold relative to clock rising edge
Address/Data output delay relative to clock rising edge
Address output valid before ALEsignal falling edge
Address output valid after ALEsignal falling edge
-
-
-
-
tHD
ns
tOV
3.0
-
ns
1
tAOAB
tAOAA
ns
1 , 2
1 , 2
-
ns
Notes :
General comment: All timing values are for interfacing synchronous devices.
General comment: All values are defined on VDDIO/2.2, unless otherw ise specified.
1. For all signals, the load is CL = 5 pF.
2. The AD bus is normally loaded w ith high capacitance. Make sure to w ork according to HW design guide lines
or simulations in order to meet the latch AC timing requirements.
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 97
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
