Electrical Specifications
AC Electrical Specifications
9.6.7
Serial Peripheral Interface (SPI) AC Timing
9.6.7.1
SPI (Master Mode) AC Timing Table
Table 44: SPI (Master Mode) AC Timing Table
SPI
Description
SCLK clock frequency
Symbol
fCK
Min
Max
Units
MHz
tCK
tCK
V/ns
ns
Notes
See Note 3
3
1
1
1
1
1
1
2
2
SCLK high time
tCH
0.46
-
SCLK low time
tCL
0.46
0.5
-2.5
8.0
8.0
0.2
5.0
-
SCLK slew rate
tSR
-
Data out valid relative to SCLK falling edge
CS active before SCLK rising edge
CS not active after SCLK rising edge
Data in setup time relative to SCLK rising edge
Data in hold time relative to SCLK rising edge
tDOV
tCSB
tCSA
tSU
2.5
-
-
-
-
ns
ns
tCK
ns
tHD
Notes :
General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 10 pF.
2. Defined from vddio/2 to vddio/2.
3. See "Reference Clocks" table for more details.
9.6.7.2
SPI (Master Mode) Test Circuit
Figure 24: SPI (Master Mode) Test Circuit
Test Point
CL
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 91
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
