Pin Information
Pin Logic
2.1
Pin Logic
Figure 2: MV78100 Interface Pin Logic Diagram
REF_CLK_SSC
PEX_CLK_P
PEX_CLK_N
REF_CLK_PT
SYSRSTn
Misc.
PEX_TX_P[3:0]
PEX_TX_N[3:0]
TCLK_OUT
TCLK_IN
PEX_RX_P[3:0]
PCI Express0/1
PEX_RX_N[3:0]
PEX0/1_ISET
PEX_TP
USB_DP
USB_DM
USB0/1/2
PEX_HSDACN
PEX_HSDACP
DEV_CSn[3:0]
DEV_BootCSn
DEV_OEn
TWSIx_SDA
TWSI
DEV_WEn[3:0]
DEV_ALE[1:0]
DEV_AD[31:0]
DEV_A[2:0]
TWSIx_SCK
Device
MPP[23:0]
MPP
DEV_READYn
DEV_BURSTn/
DEV_LASTn
UA0_RXD
GE0_TXCLKOUT
GE0_TXCLK
UA0_TXD
UART
UA1_RXD
GE0_TXD[3:0]
GE0_TXD[7:4]
UA1_TXD
GE0_TXERR
GE0_TXCTL/GE0_TXEN
GE0_RXD[3:0]
JT_CLK
JT_TDI
Gigabit Ethernet
GE0_RXD[7:4]
GE0_RXERR
GE0_RXCTL/GE0_RXDV
GE0_RXCLK
GE0_COL
JT_TDO
JTAG
JT_TMS_CPU
JT_TMS_CORE
JT_RSTn
GE_MDC
GE_MDIO
M_VREF
M_CLKOUT[2:0]
M_CLKOUTn[2:0]
M_CKE[3:0]
SATAx_TX_P
SATAx_TX_N
SATAx_RX_P
SATA0/1
M_RASn
SATAx_RX_N
SATA_USB_TP
M_CASn
SATA_USB_RES
M_WEn
M_A[14:0]
M_BA[2:0]
M_CSn[3:0]
M_DQ[63:0]
M_CB[7:0]
SDRAM
SPI_CSn
SPI_CLK
M_DQS[8:0]
M_DQSn[8:0]
M_DM[8:0]
M_ODT[3:0]
M_STARTBURST
M_STARTBURST_IN
M_PCAL
SPI
SPI_MOSI
SPI_MISO
M_NCAL
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 17
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
