MV78100
Hardware Specifications
1
Overview
The MV78100 device is part of the Discovery™ Innovation series CPU family. It provides a
single-chip, high-performance, cost-effective solution for different types of applications, such as
printers, routers, web switches, storage applications, and wireless infrastructure.
The MV78100 integrates a dual-issue, ARMv5 compatible CPU, with integrated double-precision
FPU, and 512 KB of L2 cache. The MV78100 supports the following interfaces:
32-bit/64-bit DDR2 SDRAM interface with an additional 8-bit ECC option
8/16/32-bit device bus interface
Two PCI Express x4 interfaces; each one can also act as four x1 interfaces
Three USB 2.0 ports
Two SATA II ports
Two Gigabit Ethernet MACs
Additionally, the MV78100 integrates:
A cryptographic hardware accelerator
Two XOR DMA engines
Four IDMA engines
Four 16550 compatible UARTs; one interface can support DMA-based transmit
A two channel SLIC/Codec TDM interface
SPI port
Two TWSI ports
Four general purpose timers/counters
A watchdog timer
An interrupt controller
The MV78100 architecture is based on an Mbus fabric connecting all of the units. Each unit is
connected to the Mbus via a full duplex 64-bit data path.
The Mbus architecture enables concurrency of transactions between multiple units, resulting in high
accumulative throughput. It also supports split transactions with out-of-order completion.
For low latency CPU-to-DRAM access, the MV78100 also implements a dedicated point-to-point,
128-bit full duplex data path, between the ARM compliant CPU core and the DRAM controller. The
CPU Bus Interface Unit (BIU) and DRAM controller complex run synchronously. This
implementation guarantees minimum CPU-to-DRAM latency, which is critical in embedded
applications.
MV-S104552-U0 Rev. D
Page 14
Copyright © 2008 Marvell
Document Classification: Proprietary Information
December 6, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
