List of Figures
Figure 26: SPI (Master Mode) Normal Input AC Timing Diagram......................................................................92
Figure 27: SPI (Master Mode) Opposite Output AC Timing Diagram ................................................................93
Figure 28: SPI (Master Mode) Opposite Input AC Timing Diagram...................................................................93
Figure 29: TWSI Test Circuit..............................................................................................................................95
Figure 30: TWSI Output Delay AC Timing Diagram...........................................................................................95
Figure 31: TWSI Input AC Timing Diagram .......................................................................................................96
Figure 32: Device Bus Interface Test Circuit .....................................................................................................98
Figure 33: Device Bus Interface Output Delay AC Timing Diagram ..................................................................98
Figure 34: Device Bus Interface Input AC Timing Diagram ...............................................................................99
Figure 35: JTAG Interface Test Circuit ............................................................................................................100
Figure 36: JTAG Interface Output Delay AC Timing Diagram .........................................................................101
Figure 37: JTAG Interface Input AC Timing Diagram ......................................................................................101
Figure 38: TDM Interface Test Circuit..............................................................................................................102
Figure 39: TDM Interface Output Delay AC Timing Diagram...........................................................................103
Figure 40: TDM Interface Input Delay AC Timing Diagram..............................................................................103
Figure 41: PCI Express Interface Test Circuit..................................................................................................107
10 Thermal Data (Preliminary)........................................................................................................... 116
11 Package Mechanical Dimensions ................................................................................................ 117
Figure 45: 655 Pin FCBGA Package and Dimensions ....................................................................................117
12 Part Order Numbering/Package Marking..................................................................................... 118
Figure 46: Sample Part Number ......................................................................................................................118
Figure 47: MV78100 Commercial Package Marking and Pin 1 Location.........................................................119
13 Revision History ............................................................................................................................ 120
Copyright © 2008 Marvell
MV-S104552-U0 Rev. D
Page 11
December 6, 2008, Preliminary
Document Classification: Proprietary Information
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
