Signal Description
Pin Description
Table 6:
SGMII Interface
117-TFBGA 96-BCC 128-PQFP Pin Name
Pin
Description
Pin #
Pin #
Pin #
Type
A3
A4
82
81
113
112
S_IN+
S_IN-
I
SGMII Transmit Data. 1.25 GBaud input -
Positive and Negative.
Input impedance on the S_IN± pins may be
programmed for 50 ohm or 75 ohm imped-
ance by setting register 26.6. The input
impedance default setting is determined by
the 75/50 OHM configuration pin.
A5
A6
79
80
110
109
S_CLK+
S_CLK-
I/O
SGMII 625 MHz Receive Clock.
For Serial Interface modes
(HWCFG_MODE[3:0] = 1x00) the S_CLK±
pins become Signal Detect± (SD±) inputs.
A7
A8
77
75
107
105
S_OUT+
S_OUT-
O, Z
SGMII Receive Data. 1.25 GBaud output -
Positive and Negative.
Output impedance on the S_OUT± pins may
be programmed for 50 ohm or 75 ohm
impedance by setting register 26.5. Output
amplitude can be adjusted via register
26.2:0. The output impedance default setting
is determined by the 75/50 OHM configura-
tion pin.
Copyright © 2009 Marvell
March 4, 2009, Advance
Doc. No. MV-S105540-00, Rev. --
Document Classification: Proprietary Information
Page 19
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
