88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the
RGMII interface. The MAC interface pins are 3.3V tolerant.
Table 5:
RTBI Interface
117-TFBGA 96-BCC 128-PQFP Pin Name
Pin
Description
Pin #
Pin #
Pin #
Type
E2
8
14
GTX_CLK/
TXC
I
RGMII Transmit Clock provides a 125 MHz
reference clock with ± 50 ppm tolerance. In
RTBI mode, GTX_CLK is used as TXC.
H2
G3
G2
F1
16
14
12
11
24
20
19
18
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
I
RTBI Transmit Data.
In RTBI mode, TXD[3:0] are used as
TD[3:0]. TD[3:0] run at double data rate with
bits [3:0] presented on the rising edge of
GTX_CLK, and bits [8:5] presented on the
falling edge of GTX_CLK. In this mode,
TXD[7:4] are ignored.
E1
C1
9
2
16
TX_EN/
TD4_TD9
I
RTBI Transmit Data.
In RTBI mode, TX_EN is used as TD4_TD9.
TD4_TD9 runs at a double data rate with bit
4 presented on the rising edge of GTX_CLK,
and bit 9 presented on the falling edge of
GTX_CLK.
7
RX_CLK/
RXC
O, Z
O, Z
RTBI Receive Clock provides a 125 MHz ref-
erence clock with ± 50 ppm tolerance
derived from the received data stream. In
RTBI mode, RX_CLK is used as RXC.
B3
C3
D3
B2
91
93
92
95
125
126
128
3
RXD[3]/RD[3]
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
RTBI Receive Data.
In RTBI mode, RXD[3:0] are used as
RD[3:0]. RD[3:0] runs at double data rate
with bits [3:0] presented on the rising edge of
RX_CLK, and bits [8:5] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
are ignored.
B1
94
4
RX_DV/
O, Z
RTBI Receive Data.
RD4_RD9
In RTBI mode, RX_DV is used as
RD4_RD9. RD4_RD9 runs at a double data
rate with bit 4 presented on the rising edge
of RX_CLK, and bit 9 presented on the fall-
ing edge of RX_CLK.
Doc. No. MV-S105540-00, Rev. --
Page 18
Copyright © 2009 Marvell
Document Classification: Proprietary Information
March 4, 2009, Advance
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
