LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
F
IGURE
8.
S
YMMETRIC
C
OEFFICIENT
S
ET
E
XAMPLES
8 7 6 5
8 7 6 5 4 3 2 1
7 6 5 4 3 2 1
4 3 2 1
Even-Tap, Even-Symmetric
Coefficient Set
Odd-Tap, Even-Symmetric
Coefficient Set
Even-Tap, Odd-Symmetric
Coefficient Set
F
IGURE
9.
I/D R
EGISTER
D
ATA
P
ATHS
DATA
REVERSAL
DATA
REVERSAL
DATA
REVERSAL
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
Delay Stage N–1
Delay Stage N
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
1-16
A
the I/D Register length.
The I/D Registers also facilitate using
decimation to increase the number of
filter taps. Decimation by N is
accomplished by reading the horizon-
tal filter’s output once every N clock
cycles. The device supports decima-
tion up to 16:1. With no decimation,
the maximum number of filter taps is
sixteen. When decimating by N, the
number of filter taps becomes 16N
because there are N–1 clock cycles
when the horizontal filter’s output is
not being read. The extra clock cycles
are used to calculate more filter taps.
When decimating, the I/D Registers
should be set to a length equal to the
decimation factor. For example,
when performing a 4:1 decimation,
the I/D Registers should be set to a
1-16
EVEN-TAP MODE
1-16
ALU
B
COEF 7
COEF 6
COEF 7
2
COEF 6
COEF 7
2
COEF 6
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
length of four. When not decimating
or when only one data set
(non-interleaved data) is fed into the
device, the I/D Registers should be
set to a length of one.
HSHEN enables or disables the
loading of data into the forward and
reverse I/D Registers when the device
is in Dimensionally Separate Mode
(see the HSHEN section for a full
discussion). When in Orthogonal
Mode, HSHEN also enables or
disables the loading of data into the
input register (DIN
11-0
) and the line
buffers.
It is important to note that in
Orthogonal Mode, either HSHEN or
VSHEN can disable the loading of
data into the input register (DIN
11-0
),
I/D Registers, and line buffers. Both
must be active to enable data loading
in Orthogonal Mode.
I/D Register Data Path Control
The multiplexer in the middle of the
I/D Register data path controls how
data is fed to the reverse data path.
The forward data path contains
the I/D Registers in which data
flows from left to right in the
block diagram in Figure 1. The
reverse data path contains the I/D
Registers in which data flows from
right to left. When the filter is
configured for an even number of
taps, data from the last I/D Regis-
ter in the forward data path is fed
into the first I/D Register in the
reverse data path (see Figure 9).
Video Imaging Products
7
11/08/2001-LDS.3310-H
LOGIC [ LOGIC DEVICES INCORPORATED ]
