LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
Horizontal Select
TABLE 2. CONFIGURATION REGISTER 0 – ADDRESS 200H
The word width of the horizontal
filter output is 32-bits. However, only
12-bits may be sent to the filter
output. The horizontal filter select
circuitry determines which 12-bits are
BITS
FUNCTION
DESCRIPTION
0
ALU Mode
0 : A + B
1 : B – A
1
2
Pass A
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
passed (see Table 1). The horizontal
select registers control the horizontal
select circuitry. There are sixteen
horizontal select registers. Each select
register is 5-bits wide and user-
programmable. HRSL3-0 determines
which of the sixteen horizontal select
registers are used in the horizontal
select circuitry. A value of 0 on
HRSL3-0 selects horizontal select
register 0. A value of 1 selects hori-
zontal select register 1 and so on.
HRSL3-0 may be changed every clock
cycle if desired. This allows the 12-bit
window to be changed every clock
cycle. This is useful when filtering
interleaved data. Select register
loading is discussed in the LF
Pass B
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
11-3
Reserved
Must be set to “0”
TABLE 3. CONFIGURATION REGISTER 1 – ADDRESS 201H
BITS
FUNCTION
DESCRIPTION
0
Odd-Tap Interleave Mode
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
4-1
I/D Register Length
0000: 1 Register
0001: 2 Registers
0010: 3 Registers
0011: 4 Registers
0100: 5 Registers
0101: 6 Registers
0110: 7 Registers
0111: 8 Registers
1000: 9 Registers
1001: 10 Registers
1010: 11 Registers
1011: 12 Registers
1100: 13 Registers
1101: 14 Registers
1110: 15 Registers
1111: 16 Registers
InterfaceTM section.
Horizontal Limiting
An output limiting function is
provided for the output of the
horizontal filter. The horizontal limit
registers determine the valid range of
output values when limiting is
enabled (Bit 1 in Configuration
Register 5). There are sixteen 24-bit
horizontal limit registers. HRSL3-0
determines which horizontal limit
register is used during the limit
operation. A value of 0 on HRSL3-0
selects horizontal limit register 0. A
value of 1 selects horizontal limit
register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed to
the limiting circuitry is less than the
lower limit, the lower limit value is
passed as the filter output. If the
value fed to the limiting circuitry is
greater than the upper limit, the
upper limit value is passed as the
filter output. HRSL3-0 may be
5
6
Horizontal Tap Number
Horizontal Data Reversal
Reserved
0 : Even Number of Taps
1 : Odd Number of Taps
0 : Data Reversal Enabled
1 : Data Reversal Disabled
11-7
Must be set to “0”
(see Figure 11). Each round register is on HRSL3-0 selects horizontal round
32-bits wide and user-programmable. register 0. A value of 1 selects hori-
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be
programmed into the round registers, rounding algorithm to be changed
the device can support complex
rounding algorithms as well as
zontal round register 1 and so on.
HRSL3-0 may be changed every clock
cycle if desired. This allows the
every clock cycle. This is useful when
filtering interleaved data. If rounding
standard Half-LSB rounding. HRSL3- is not desired, a round register should
0 determines which of the sixteen be loaded with 0 and selected as the
horizontal round registers are used in register used for rounding. Round
changed every clock cycle if desired.
This allows the limit range to be
the rounding operation. A value of 0
register loading is discussed in the LF
InterfaceTM section.
Video Imaging Products
11/08/2001-LDS.3310-H
9
LOGIC [ LOGIC DEVICES INCORPORATED ]
