LF3310
DEVICES INCORPORATED
Horizontal / Vertical Digital Image Filter
TABLE 8. HCF/VCF11-9 DECODE
11 10 9 DESCRIPTION
TABLE 9. HRZ. ROUND REGISTERS
TABLE 12. VRT. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
REGISTER
ADDRESS (HEX)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Coefficient Banks
0
1
800
801
0
1
A00
A01
Configuration Registers
Horizontal Select Registers
Vertical Select Registers
Horizontal Round Registers
Vertical Round Registers
Horizontal Limit Registers
Vertical Limit Registers
14
15
80E
80F
14
15
A0E
A0F
TABLE 10. HRZ. SELECT REGISTERS
TABLE 13. VRT. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
REGISTER
ADDRESS (HEX)
Vertical Rounding
0
1
400
401
0
1
600
601
The vertical filter output may be
rounded by adding the contents of
one of the sixteen vertical round
registers to the vertical filter output
(see Figure 11). Each round register is
32-bits wide and user-programmable.
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be
14
15
40E
40F
14
15
60E
60F
TABLE 11. HRZ. LIMIT REGISTERS
REGISTER
TABLE 14. VRT. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
ADDRESS (HEX)
programmed into the round registers,
the device can support complex
rounding algorithms as well as
0
1
C00
C01
0
1
E00
E01
standard Half-LSB rounding.
VRSL3-0 determines which of the
sixteen vertical round registers are
used in the rounding operation. A
value of 0 on VRSL3-0 selects vertical
round register 0. A value of 1 selects
vertical round register 1 and so on.
VRSL3-0 may be changed every clock
cycle if desired. This allows the
rounding algorithm to be changed
every clock cycle. This is useful when
filtering interleaved data. If rounding
is not desired, a round register should
be loaded with 0 and selected as the
register used for rounding. Round
register loading is discussed in the LF
InterfaceTM section.
14
15
C0E
C0F
14
15
E0E
E0F
register is 5-bits wide and
user-programmable. VRSL3-0 deter-
mines which of the sixteen vertical
select registers are used in the vertical the limit operation. A value of 0 on
select circuitry. A value of 0 on VRSL3-0 selects vertical limit register
VRSL3-0 selects vertical select register 0. A value of 1 selects vertical limit
0. A value of 1 selects vertical select
register 1 and so on. VRSL3-0 may be
changed every clock cycle if desired.
This allows the 12-bit window to be
changed every clock cycle. This is
useful when filtering interleaved
data. Select register loading is
discussed in the LF InterfaceTM
section.
are sixteen 24-bit vertical limit
registers. VRSL3-0 determines which
vertical limit register is used during
register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed to
the limiting circuitry is less than the
lower limit, the lower limit value is
passed as the filter output. If the
value fed to the limiting circuitry is
greater than the upper limit, the upper
limit value is passed as the filter output.
VRSL3-0 may be changed every clock
cycle if desired. This allows the limit
range to be changed every clock cycle.
This is useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
InterfaceTM section.
Vertical Select
The word width of the vertical filter
output is 32-bits. However, only
12-bits may be sent to the filter
output. The vertical filter select
circuitry determines which 12-bits are
passed (see Table 1). The vertical
select registers control the vertical
select circuitry. There are sixteen
vertical select registers. Each select
Vertical Limiting
An output limiting function is pro-
vided for the output of the vertical
filter. The vertical limit registers
determine the valid range of output
values when limiting is enabled (Bit 0
in Configuration Register 5). There
Video Imaging Products
11/08/2001-LDS.3310-H
11
LOGIC [ LOGIC DEVICES INCORPORATED ]
