L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
F
IGURE
4C.
FTAB = 1, FTF = 0
From
To
Clock
©
F
A, B
©
Other
C
0
©
Other
S
4
-S
0
©
Other
A, B
Setup time
C
0
Setup time
S
4
-S
0
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
=
=
=
=
=
=
=
=
=
Calculated Specification Limit
Same as 16-bit case
(A, B
©
C
16
) + (C
0
©
Out)
(C
0
©
C
16
) + (C
0
©
Out)
(S
4
-S
0
©
C
16
) + (C
0
©
Out)
(A, B
©
C
16
) + (C
0
Setup time)
(C
0
©
C
16
) + (C
0
Setup time)
(S
4
-S
0
©
C
16
) + (C
0
Setup time)
Same as 16-bit case
(Clock
©
C
16
) + (C
0
Setup time)
A
31
-A
16
B
31
-B
16
A
15
-A
0
B
15
-B
0
C
0,
S
4
–S
0
A
F
B
C
0
A
C
16
F
B
C
0
D
Q
CLOCK
16
D
Q
CLOCK
MOST
SIGNIFICANT
SLICE
16
F
31
-F
16
F
15
-F
0
LEAST
SIGNIFICANT
SLICE
F
IGURE
4D.
FTAB = 1, FTF = 1
From
To
A, B
©
F
A, B
©
Other
C
0
©
F
C
0
©
Other
S
4
-S
0
©
F
S
4
-S
0
©
Other
A, B
Setup time
C
0
Setup time
S
4
-S
0
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
=
=
=
=
=
=
=
=
=
=
=
Calculated Specification Limit
(A, B
©
C
16
) + (C
0
©
F)
(A, B
©
C
16
) + (C
0
©
Out)
(C
0
©
C
16
) + (C
0
©
F)
(C
0
©
C
16
) + (C
0
©
Out)
(S
4
-S
0
©
C
16
) + (C
0
©
F)
(S
4
-S
0
©
C
16
) + (C
0
©
Out)
(A, B
©
C
16
) + (C
0
Setup time)
(C
0
©
C
16
) + (C
0
Setup time)
(S
4
-S
0
©
C
16
) + (C
0
Setup time)
Same as 16-bit case
(Clock
©
C
16
) + (C
0
Setup time)
A
31
-A
16
B
31
-B
16
A
15
-A
0
B
15
-B
0
C
0,
S
4
–S
0
A
F
B
C
0
A
C
16
16
F
B
C
0
MOST
SIGNIFICANT
SLICE
16
F
31
-F
16
F
15
-F
0
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
4
08/16/2000–LDS.383-E
LOGIC [ LOGIC DEVICES INCORPORATED ]
