L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
*
L4C383-15
To Output
L4C383-20
From Input
F15-F0
N
OVF, Z C16 F15-F0
N
OVF, Z C16
FTAB = 0, FTF = 0
Clock
C0
11
—
—
20
—
18
20
14
20
20
14
18
11
—
—
15
—
14
15
13
15
15
13
14
S4-S0
FTAB = 0, FTF = 1
Clock
C0
20
18
20
20
—
18
20
14
20
20
14
18
15
14
15
15
—
14
15
13
15
15
13
14
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
—
11
—
—
16
—
—
18
20
—
14
20
17
—
14
18
—
11
—
—
14
—
—
14
15
—
13
15
14
—
13
14
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
20
20
18
20
16
20
—
18
20
20
14
20
17
20
14
18
15
15
14
15
14
15
—
14
15
15
13
15
14
15
13
14
C0
S4-S0
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
*
L4C383-20
FTAB = 0 FTAB = 1
Setup Hold Setup Hold Setup Hold Setup Hold
L4C383-15
FTAB = 0 FTAB = 1
Input
A15-A0, B15-B0
C0
5
12
15
5
0
0
0
0
14
12
15
5
0
0
0
0
5
10
12
5
0
0
0
0
12
10
12
5
0
0
0
0
S4-S0
ENA, ENB, ENF
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
*
*
L4C383-20 L4C383-15
L4C383-20 L4C383-15
Minimum Cycle Time
Highgoing Pulse
Lowgoing Pulse
tENA
tDIS
8
8
6
6
18
5
14
4
5
4
*DISCONTINUED SPEED GRADE
Arithmetic Logic Units
08/16/2000–LDS.383-E
7
LOGIC [ LOGIC DEVICES INCORPORATED ]
