L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
T
ABLE
2.
ALU S
TATUS
F
LAGS
for i = 0 ... 15
for i = 0 ... 15
T
ABLE
1. A
LU
F
UNCTIONS
S
4
-S
0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
FUNCTION
A + B + C
0
A OR B
A + B + C
0
A + B + C
0
A + C
0
A OR F
A – 1 + C
0
A + C
0
A + F + C
0
A OR F
A + F + C
0
A + F + C
0
F + B + C
0
A OR B
F + B + C
0
F + B + C
0
A XOR B
A AND B
A AND B
A XNOR B
A XOR F
A AND F
A AND F
ALL 1's + C
0
B + C
0
A AND B
B + C
0
B – 1 + C
0
F + C
0
A OR B
F – 1 + C
0
F + C
0
Bit Carry Generate = g
i
= A
i
B
i
Bit Carry Propagate = p
i
= A
i
+ B
i
P
0
= p
0
P
i
= p
i
(P
i–1
)
and
G
0
= g
0
G
i
= g
i
+ p
i
(G
i–1
)
C
i
= G
i–1
+ P
i–1
(C
0
)
then
C
16
OVF
Zero
N =
= G
15
+ P
15
C
0
= C
15
XOR C
16
= All Output Bits Equal Zero
Sign Bit of ALU Operation
for i = 1 ... 15
for i = 1 ... 15
for i = 1 ... 15
OUTPUT REGISTER
The output of the ALU drives the input of
a 16-bit register. This rising-edge-
triggered register is clocked by the same
clock as the input registers. When the
ENF control is LOW, data from the ALU
will be clocked into the output register.
By disabling the output register, interme-
diate results can be held while loading
new input operands. Three-state drivers
controlled by the OE input allow the
L4C383 to be configured in a single
bidirectional bus system.
The output register can be bypassed by
asserting the FTF control signal (FTF =
HIGH). When the FTF control is asserted,
output data is routed around the output
register, however, it continues to function
normally via the ENF control. The
contents of the output register will again
be available on the output pins if FTF is
released.
CASCADING THE L4C383
Cascading the L4C383 to 32 bits is
accomplished simply by connecting the
C
16
output of the least significant slice to
the C
0
input of the most sig-nificant slice.
The S
4
-S
0
, ENA, ENB, and ENF lines are
common to both devices. The Zero output
flags should be logically ANDed to
produce the Zero flag for the 32-bit result.
The OVF and C
16
outputs of the most
significant slice are valid for the 32-bit
result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from the
input of interest to the C
16
output of the
lower slice. Add this number to the delay
from the C
0
input of the upper slice to the
output of interest (of the C
0
setup time, if
the F register is used). The sum gives the
overall input-to-output delay (or setup
time) for the 32-bit configuration. This
method gives a conservative result, since
the C
16
output is very lightly loaded.
Formulas for calculation of all critical
delays for a 32-bit system are shown in
Figures 4A through 4D.
Cascading to greater than 32 bits can be
accomplished by simply connecting the
C
16
output of each slice to the C
0
input of
the next more significant slice.
Propagation delays are calculated as
for the 32-bit case, except that the C
0
to C
16
delays for all intermediate slices
must be added to the overall delay for
each path.
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
Arithmetic Logic Units
2
08/16/2000–LDS.383-E
LOGIC [ LOGIC DEVICES INCORPORATED ]
