LTC3642
APPLICATIONS INFORMATION
3. Keep the switching node, SW, away from all sensitive
smallsignalnodes.Therapidtransitionsontheswitching
node can couple to high impedance nodes, in particular
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3642. Check the following in your layout:
V , and create increased output ripple.
FB
4. Floodallunusedareaonalllayerswithcopper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
1. Large switched currents flow in the power switches
and input capacitor. The loop formed by these compo-
nents should be as small as possible. A ground plane
is recommended to minimize ground impedance.
DC net (V , V , GND or any other DC rail in your
IN OUT
system).
2. Connect the (+) terminal of the input capacitor, C , as
IN
close as possible to the V pin. This capacitor provides
IN
the AC current into the internal power MOSFETs.
TYPICAL APPLICATIONS
Efficiency vs Load Current
L1
94
220ꢀH
V
= 10V
IN
V
V
IN
OUT
V
SW
LTC3642
IN
5V TO 45V
5V
R
= 750k
C
R1
C
93
92
91
90
89
88
SET
IN
OUT
4.7ꢀF
4.2M
100ꢀF
R
= 500k
SET
RUN
HYST
V
FB
R2
800k
I
OPEN
SET
I
SS
SET
C
GND
SS
R
SET
47nF
3642 F10a
C
C
: TDK C5750X7R2A475MT
: AVX 1812D107MAT
IN
OUT
L1: TDK SLF7045T-221MR33-PF
Figure 10. High Efficiency 5V Regulator
1
10
LOAD CURRENT (mA)
100
3642 F10b
3.3V, 50mA Regulator with Peak Current Soft-Start, Small Size
Soft-Start Waveforms
L1
47ꢀH
V
OUT
V
IN
V
SW
LTC3642
RUN
3.3V
IN
4.5V TO 24V
C
R1
50mA
C
OUTPUT VOLTAGE
1V/DIV
IN
1ꢀF
OUT
294k
10ꢀF
V
FB
R2
93.1k
I
SET
SS
HYST
GND
3642 TA02a
C
INDUCTOR CURRENT
20mA/DIV
SS
0.1ꢀF
C
C
: TDK C3216X7R1E105KT
: AVX 08056D106KAT2A
IN
OUT
3642 TA03b
2ms/DIV
L1: TAIYO YUDEN CBC2518T470K
3642f
16
Linear [ Linear ]
