LT1375/LT1376
U
W U U
APPLICATIONS INFORMATION
8.0
Compensation section for a discussion of an entirely
different cause of subharmonic switching before assum-
ing that the cause is insufficient slope compensation.
ApplicationNote19hasmoredetailsonthetheoryofslope
compensation.
(A) MINIMUM VOLTAGE
TO START WITH
7.5
7.0
6.5
6.0
5.5
5.0
STANDARD CIRCUIT
(A)
(B)
(B) MINIMUM VOLTAGE
TO RUN WITH
STANDARD CIRCUIT
(C)
(C) MINIMUM VOLTAGE
TO START WITH
PNP
There is a sync-supply sequence issue with the LT1375. If
power is supplied to the regulator after the external sync
signal is supplied, the regulator may not start. This is
caused by the internal frequency foldback condition that
occurs when the FB pin is below 1V (see block diagram
description in the data sheet). The oscillator tries to run at
100kHz when the FB pin is below 1V, and a high frequency
sync signal will then create an extremely low amplitude
oscillatorwaveform.Thisamplitudemaybesolowthatthe
switch logic is not triggered to create switching. Under the
normal regulated condition, the oscillator runs at much
higher amplitude with plenty of drive for the switch logic.
Notethatforfixedvoltageparts, theFBpinisreplacedwith
a SENSE pin, and the voltage divider resistors are internal.
In that case, the FB pin drops below 1V when the output
voltage is less than 40% of its regulated value.
(D)
(D) MINIMUM VOLTAGE
TO RUN WITH
PNP
0.001
0.01
0.1
1
1375/76 F09
LOAD CURRENT (A)
Figure 9. Minimum Input Voltage
D1
1N914
C2
0.1µF
D3
1N914
L1
BOOST
OUTPUT
INPUT
V
V
SW
IN
Q1
2N3905
LT1376-5
+
SENSE
GND
V
C
+
There are no sequence problems if the power supply for
the sync signal comes from the output of the LT1375. If
this is not the case, and the sync signal could be present
when power is applied to the regulator, a gate should be
used to block sync signals as shown in Figure 11. Any
other technique which prevents sync signals when the
regulator output is low will work just as well. It does not
matter whether the sync signal is forced high or low; the
internal circuitry is edge triggered.
C1
C
C
1375/76 F10
Figure 10. Reducing Minimum Input Voltage
SYNCHRONIZING (Available on LT1375 Only)
The LT1375 has the BIAS pin replaced with a SYNC pin,
which is used to synchronize the internal oscillator to an
external signal. It is directly logic compatible and can be
driven with any signal between 10% and 90% duty cycle.
The synchronizing range is equal to initial operating fre-
quency up to 900kHz. This means that minimum practical
sync frequency is equal to the worst-case high self-
oscillating frequency (560kHz), not the typical operating
frequency of 500kHz. Caution should be used when syn-
chronizing above 700kHz because at higher sync frequen-
cies the amplitude of the internal slope compensation
used to prevent subharmonic switching is reduced. This
type of subharmonic switching only occurs at input volt-
ages less than twice output voltage. Higher inductor
values will tend to eliminate problems. See Frequency
V
IN
LT1375
V
OUT
SYNC
1375/76 F11
Figure 11. Gating the Sync Signal
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also
13756fd
19
Linear [ Linear ]
