LT1375/LT1376
U
W U U
APPLICATIONS INFORMATION
Quiescent current loss:
Keep in mind that this procedure does not take initial
component tolerance into account. You should see fairly
cleanresponseunderallloadandlineconditionstoensure
that component variations will not cause problems. One
note here: according to Murphy, the component most
likely to be changed in production is the output capacitor,
because that is the component most likely to have manu-
facturer variations (in ESR) large enough to cause prob-
lems. It would be a wise move to lock down the sources of
the output capacitor in production.
2
⎛
⎞
V
0.002
⎜
⎝
⎟
⎠
(
)
OUT
P = V 0.001 + V
0.005 +
(
)
(
)
Q
IN
OUT
V
IN
RSW = Switch resistance (≈0.4)
16ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with VIN = 10V, VOUT = 5V and IOUT = 1A:
0.4 1 2 5
Apossibleexceptiontothe“cleanresponse”ruleisatvery
light loads, as evidenced in Figure 17 with ILOAD = 50mA.
Switching regulators tend to have dramatic shifts in loop
response at very light loads, mostly because the inductor
current becomes discontinuous. One common result is
very slow but stable characteristics. A second possibility
is low phase margin, as evidenced by ringing at the output
with transients. The good news is that the low phase
margin at light loads is not particularly sensitive to com-
ponentvariation, soifitlooksreasonableunderatransient
test, it will probably not be a problem in production. Note
that frequency of the light load ringing may vary with
componenttolerancebutphasemargingenerallyhangsin
there.
(
)( ) ( )
−9
3
⎛
⎞
⎠
⎛
⎞
⎠
PSW
=
+ 16 •10
1 10 500 •10
( )( )
⎝
⎝
10
= 0.2 + 0.08 = 0.28W
2
5
0.008 + 1/75
( ) (
)
PBOOST
=
= 0.053W
10
2
5
( ) (
0.002
)
P = 10 0.001 + 5 0.005 +
= 0.04W
(
)
(
)
Q
10
Total power dissipation is 0.28 + 0.053 + 0.04 = 0.37W.
Thermal resistance for LT1376 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about120°C/W. Noplanewillincreaseresistancetoabout
160°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
THERMAL CALCULATIONS
Power dissipation in the LT1376 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current,andinputquiescentcurrent.Thefollowingformu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
TJ = TA + θJA (PTOT
)
With the SO-8 package (θJA = 120°C/W), at an ambient
temperature of 70°C,
TJ = 70 + 120 (0.37) = 114.4°C
Switch loss:
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
2
RSW OUT
I
V
OUT
(
) (
)
P
=
+ 16ns I
V
f
(
OUT)( )( )
SW
IN
V
IN
Boost current loss:
2
VOUT 0.008 + I
/ 75
(
)
OUT
PBOOST
=
V
IN
13756fd
23
Linear [ Linear ]
