LTM4641
APPLICATIONS INFORMATION—POWER SUPPLY FEATURES
conceivably approach f
at start-up, however briefly
TEꢁP, OTBH and Overteꢃperature Protection
MAX
(see Equation 8). When biasing DRV from INTV in
CC
CC
AsseeninFigure1,aresistor-NTC-dividernetworkformed
such applications, INTV may require additional bypass
CC
between 1V
and SGND generates TEMP, an analog
REF
capacitance to ride through the resulting current surge on
temperature indicator pin. The pin nominally measures
~0.98V at 25°C and colder, and ~585mV at 125°C. A
graph of the relationship between junction temperature,
NTC resistance, and TEMP voltage is found in Figure 10.
DRV . INTV can by bypassed with up to 4.7μF ( 20%
CC
CC
tolerance) of external decoupling capacitance.
1V
REF
The TEMP pin also connects indirectly to a comparator
input whose output can pull HYST low to inhibit switch-
ing action. If TEMP falls below 438mV, corresponding
to a junction temperature of ~147°C, switching action
is inhibited. If OTBH is logic low when TEMP falls below
438mV, a latchoff overtemperature event is registered.
Restarting regulation after a latchoff event has occurred
is explained in detail in the Start-Up/Shutdown section.
If OTBH is open circuit when TEMP falls below 438mV, a
nonlatching overtemperature event is registered: switch-
ing action can resume when the units cools off and the
TEMP pin rises above 514mV, corresponding to a junction
temperature of ~136°C.
A housekeeping IC internal to the LTM4641 generates
a 1V 1.5% reference voltage. This voltage reference is
generatedindependentofthecontrolIC’s600mVbandgap
voltage. The 1V should only be used to alter the OV
REF
PGM
thresholdprogrammingvoltageforthefastOOVcompara-
tor (see Fast Output Overvoltage Comparator Threshold
section) or to implement an auxiliary overtemperature
detector with an NTC having ultrahigh resistance (470k at
25°C,B-value<5000K)—inthemannershowninFigure47.
Loading 1V beyond 100μA is not recommended.
REF
1V
must become established quickly at start-up to
REF
properlybiasOV
,andthereforenoexternalcapacitance
PGM
should be applied to this pin. To minimize disturbance to
the OV voltage, dynamic step-loading of the 1V is
The LTM4641’s overtemperature protection feature is in-
tended to protect the device during momentary overload
conditions.RecognizethattheLTM4641isratedfor125°C
junction,absolutemaximum,andthatjunctiontemperature
exceeds125°Cwhenovertemperatureprotectionisactive.
Continuous operation above the specified maximum op-
erating junction temperature may impair device reliability.
PGM
REF
not recommended. Figure 9 shows the step response of
1V to a 0μA to 100μA step load with 100A/s slew rates,
REF
and the resulting impact to OV
’s voltage waveform.
PGM
1V
REF
100mV/DIV
The overtemperature protection circuit can be disabled
AC-COUPLED
by connecting TEMP to 1V . With moderate linear cir-
REF
I
1VREF
50µA/DIV
cuit analysis, the information in Figure 10 and Figure 62
(Appendix A) can be used to alter the overtemperature
inception and recovery thresholds. If desired, the thresh-
olds can be increased by applying a resistor from TEMP to
OV
PGM
10mV/DIV
AC-COUPLED
4641 F09
20µs/DIV
1V , or decreased by applying a resistor from TEMP to
REF
SGND. The overtemperature comparator contains built-in
filtering, yielding glitch immunity characteristics shown
in Figure 12.
Figure 9. Response of 1VREF to 0μA ⇔ 100μA Load Steps
Applied at 100A/s—and Resulting Disturbance and Recovery
of OVPGꢁ. Figure 43 Circuit. Do Not Load 1VREF Arbitrarily
4641f
28
Linear [ Linear ]
