LTM4641
PIN FUNCTIONS
SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; ꢁ1-ꢁ3): Signal
Ground Pins. This is the return ground path for all analog
control and low power circuitry. SGND is tied to GND in-
ternal to the µModule regulator in a manner that promotes
thebestinternalsignalintegrity—therefore, SGNDshould
not be connected to GND in the user’s PCB layout. See
the Layout Checklist/Example section of the Applications
Information section for more information pertaining to
SGNDandlayout. AllSGNDpinsareelectricallyconnected
to each other, internally.
may be deasserted when TEMP subsequently exceeds
514mV (nominally corresponding to a cool-off hysteresis
of~10°C), dependingontheOTBHsetting. (SeeOTBHand
the Applications Information section.)
To disable the µModule regulator’s overtemperature
shutdown feature, connect the TEMP and 1V pins. The
REF
thermal shutdown inception threshold can also be modi-
fied, see the Applications Information section.
IOVRETRY(A6):NonlatchingInputOvervoltageThreshold
Programming Pin. The LTM4641 pulls HYST low to inhibit
regulation of its output voltage when IOVRETRY exceeds
0.5V. The LTM4641 can resume switching action when
IOVRETRYisbelow0.5V.Ifnononlatchinginputovervoltage
shutdown behavior is desired, connect this pin to SGND.
Do not leave this pin open circuit.
HYST (A4): Input Undervoltage Hysteresis Programming
Pin. Normally used as an output, but can be used as an
input. If the LTM4641’s inherent, default undervoltage
lockout (UVLO) settings are satisfactory, 4.5V
IN(RISING,
, HYST can be left electrically
and 4V
MAX)
IN(FALLING, MAX)
open circuit. See the Applications Information section to
customize the LTM4641’s UVLO thresholds.
GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8;
F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11-
K12; L4-L6; ꢁ4-ꢁ6): Power ground pins for input and
output returns. See the Layout Checklist/Example section
of the Applications Information section. All GND pins are
electrically connected to each other, internally.
HYSTisalogic-highoutputwithmoderatepull-upstrength
that commands LTM4641’s internal control IC to regulate
the module’s output voltage when conditions on the RUN,
UVLO, OVLO, IOVRETRY, TEMP, CROWBAR, INTV and
CC
DRV pins permit it (any recent latchoff events notwith-
CC
UVLO (B4): Input Undervoltage Lockout Programming
Pin. The LTM4641 pulls HYST low to inhibit regulation
of its output voltage whenever UVLO is less than 0.5V.
The LTM4641 can resume switching action when UVLO
exceeds 0.5V. Do not leave this pin open circuit.
standing,otherwiseOTBHandLATCHcanalsoplayarole).
Whenafaultconditionisdetected,internalcircuitry(M
;
HYST
see Figure 1) drives HYST logic low and the LTM4641’s
output is turned off. HYST can be used as a fault-indicator.
See the Applications Information section.
If the LTM4641’s default UVLO settings are used,
HYST is pulled low when the RUN pin is pulled low, via
an internal Schottky diode. HYST can be driven low by
external open-collector/open-drain circuitry directly—as
an alternate to the RUN pin interface. However, external
circuitry should never drive HYST high, since doing so
(indiscriminately) could cause thermal overstress to
4.5V
and 4V
, then the UVLO
IN(RISING, MAX)
pin should be electrically connected to 1V
IN(FALLING, MAX)
or INTV .
CC
REF
Otherwise, see HYST and the Applications Information
section for using a resistor-divider network to implement
personalized UVLO rising and UVLO falling settings.
M
, when M
is on.
HYST
HYST
OVLO(B5):InputOvervoltageLatchoffProgrammingPin.
LTM4641 pulls HYST low to inhibit regulation of its output
voltage when OVLO exceeds 0.5V. If OVLO subsequently
falls below 0.5V, the module’s output remains latched
off; the LTM4641 cannot resume regulation of the output
TEꢁP (A5): Power Stage Temperature Indicator and
OvertemperatureDetectionPin.Whenleftelectricallyopen
circuit,TEMP’svoltagevariesaccordingtoaninternalNTC
(negative temperature coefficient) thermistor, residing in
close proximity to LTM4641’s power stage. When TEMP
falls below 438mV (corresponding to a thermistor and
power stage temperature of ~145°C), the LTM4641 pulls
HYST low to inhibit regulation of its output voltage. HYST
voltage until either the LATCH pin is toggled high or V
INL
is power cycled. If input overvoltage latchoff behavior is
not desired, electrically short this pin to SGND. Do not
leave this pin open circuit.
4641f
10
Linear [ Linear ]
