LG Semicon
GM72V66841CT/CLT
Mode Register Set to Bank-Active Command
Interval : The interval between setting the mode
register and executing a bank-active command
must be no less than tRSA.
CLK
MRS
ACTV
Command
CODE
BS & ROW
Address
(A0-A13)
tRSA
Mode
Bank
Register Set
Active
DQM Control
DQM Control (GM72V661641CT/CLT)
(GM72V66841CT/CLT,GM72V66441CT)
The DQMU and DQML mask the upper and
lower bytes of DQ data, respectively. The timing
of DQMU/DQML is different during reading and
writing.
The DQM mask DQ data. The timing of DQM is
different during reading and writing.
Reading: When data is read, the output buffer
can be controlled by DQM. By setting DQM to
Low, the output buffer becomes Low-Z, enabling
data output. By setting DQM to High, the output
buffer becomes High-Z, and the corresponding
data is not output. However, internal reading
operations continue. The latency of DQM during
reading is 2.
Reading: When data is read, the output buffer
can be controlled by DQMU/DQML. By setting
DQMU/DQML to Low, the output buffer
becomes Low-Z, enabling data output. By setting
DQMU/DQML to High, the output buffer
becomes High-Z, and the corresponding data is
not output. However, internal reading operations
continue. The latency of DQMU/DQML during
reading is 2.
Writing: Input data can be masked by DQM. By
setting DQM to Low, data can be written. In
addition, when DQM is set to High, the
corresponding data is not written, and the
previous data is held. The latency of DQM during
writing is 0.
Writing: Input data can be masked by
DQMU/DQML. By setting DQMU/DQML to
Low, data can be written. In addition, when
DQMU/DQML is set to High, the corresponding
data is not written, and the previous data is held.
The latency of DQMU/DQML during writing
is 0.
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