LG Semicon
GM72V66841CT/CLT
Burst Length
CLK
tRCD
Active
Read
Command
Address
Column
Row
out 0
BL = 1
BL = 2
BL = 4
out 0 out 1
out 0 out 1 out 2 out 3
Dout
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0-1
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0 out 1
BL = Full Page
BL = Burst Length
CAS Latency = 2
Write Operation
2. Single write:
Burst write or single write mode is selected by
the OPCODE(A13, A12,A11, A10, A9, A8) of
the mode register.
A single write operation is enabled by setting
OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column
address (AY0 to AY8; GM72V66841CT/CLT) and
the bank select address (A12/A13) specified by
the write command set cycle without regard to
the burst length setting. (The latency of data
input is 0.)
1. Burst write:
A burst write operation is enabled by setting
OPCODE(A9, A8) to (0, 0). A burst write starts
in the same cycle as a write command set. (The
latency of data input is 0.) The burst length can
be set to 1, 2, 4, 8 and full page, like burst read
operations. The write start address is specified
by the column address (AY0 to AY8;
GM72V66841CT/CLT) and the bank select address
(A12/A13) at the write command set cycle.
18
LG [ LG SEMICON CO.,LTD. ]
