LG Semicon
GM72V66841CT/CLT
Mode Register Configuration
The mode register is set by the input to the
address pins (A0 to A13) during mode register
set cycles. The mode register consists of five
sections, each of which is assigned to address
pins.
Burst read and SINGLE WRITE:
Data is only written to the column address
specified during the write cycle, regardless of the
burst length.
A7:
A13, A12, A11, A10, A9, A8: (OPCODE):
Keep this bit Low at the mode register set cycle.
A6, A5, A4: (LMODE):
These pins specify the CAS latency.
A3: (BT):
The synchronous DRAM has two types of write
modes. One is the burst write mode, and the
other is the single write mode. These bits specify
write mode.
Burst read and BURST WRITE:
A burst type is specified . When full-page burst is
performed, only "sequential" can be selected.
Burst write is performed for the specified burst
length starting from the column address specified
in the write cycle.
A2, A1, A0: (BL):
These pins specify the burst length.
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE
0
LMODE
BT
BL
A6 A5 A4 CAS Latency
A3 Burst Type
Burst Length
BT=0 BT=1
A2 A1 A0
0
0
0
0
1
0
0
0
1
R
R
2
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
1
0
1
1
3
4
4
X
X
R
8
8
R
R
R
R
R
R
R
A13 A12 A11 A10 A9 A8
Write mode
F.P.
0
0
0
0
1
1
0
1
0
1
Burst read and BURST WRITE
0
0
X
X
X
X
X
X
X
X
R
F.P. = Full Page
(512:GM72V66841CT/CLT)
R is Reserved (inhibit)
X: 0 or 1
X
X
X
X
Burst read and SINGLE WRITE
R
15
LG [ LG SEMICON CO.,LTD. ]
