LG Semicon
GM72V66841CT/CLT
From [READ]
From [WRITE]
To [DESL], [NOP]: These commands
continue read operations until the burst
operation is completed.
To [DESL], [NOP]: These commands
continue write operations until the burst
operation is completed.
To [BST]: This command stops a full-page
To [BST]: This command stops a full-page
burst.
burst.
To [READ], [READ A]: Data output by the
previous read command continues to be
output. After CAS latency, the data output
resulting from the next command will start.
To [READ], [READ A]: These commands
stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands
stop a burst and start the next write cycle.
To [WRIT], [WRIT A]: These commands
stop a burst read, and start a write cycle.
To [ACTV]: This command makes the
other bank active. (However, an interval of
To [ACTV]: This command makes other
banks bank-active. (However, an interval of
t
RRD is required.) Attempting to make the
currently active bank active results in an
illegal command.
tRRD is required.) Attempting to make the
currently active bank active results in an
illegal command.
To [PRE], [PALL]: These commands stop
burst write and the synchronous DRAM
then enters Precharge mode.
To [PRE], [PALL]: These commands stop a
burst read, and the synchronous DRAM
enters Precharge mode.
From [WRITE with AUTO-Precharge]
To [DESL], [NOP]: These commands
continue write operations until the burst
operation is completed, and the synchronous
DRAM then enters Precharge mode.
From [READ with AUTO-Precharge]
To [DESL], [NOP]: These commands
continue read operations until the burst
operation is completed, and the synchronous
DRAM then enters Precharge mode.
To [ACTV]: This command makes the other
bank active. (However, an interval of tRC is
required.) Attempting to make the currently
active bank active results in an illegal
command.
To [ACTV]: This command makes other
banks bank-active. (However, an interval of
t
RRD is required.) Attempting to make the
currently active bank active results in an
illegal command.
From [REFRESH]
To [DESL], [NOP], [BST]: After an auto-
refresh cycle (after tRC), the synchronous
DRAM automatically enters the Idle state.
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