To
I/O
Cell
From
Logic
Allocator
n
To
I/O
Cell
From
Logic
Allocator
n
To Switch
Matrix
To Switch
Matrix
b. Combinatorial, active low
a. Combinatorial, active high
From
Logic
Allocator
From
Logic
Allocator
To
I/O
Cell
To
I/O
Cell
n
n
AP
AR
AP
D
Q
D
Q
CLK
0
CLK
0
AR
CLK
n
CLK
n
To Switch
Matrix
To Switch
Matrix
c. D-type register, active high
d. D-type register, active low
From
Logic
Allocator
From
Logic
Allocator
To
I/O
Cell
To
I/O
Cell
n
n
AP
AR
AP
Q
T
Q
T
CLK
0
CLK
0
AR
CLK
n
CLK
n
To Switch
Matrix
To Switch
Matrix
f. T-type register, active low
e. T-type register, active high
From
Logic
Allocator
From
Logic
Allocator
To
I/O
Cell
n
AP
n
AP
To
I/O
Cell
L
Q
L
Q
CLK
0
CLK
0
G
G
AR
AR
CLK
n
CLK
n
To Switch
Matrix
To Switch
Matrix
h. Latch, active low (MACH 2 only)
g. Latch, active high (MACH 2 only)
14051K-005
Figure 4. Output Macrocell Configurations
MACH 1 & 2 Families
9
LATTICE [ LATTICE SEMICONDUCTOR ]
