欢迎访问ic37.com |
会员登录 免费注册
发布采购

MACH131SP-15VC 参数 Datasheet PDF下载

MACH131SP-15VC图片预览
型号: MACH131SP-15VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能EE CMOS可编程逻辑 [High-Performance EE CMOS Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 48 页 / 1080 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号MACH131SP-15VC的Datasheet PDF文件第9页浏览型号MACH131SP-15VC的Datasheet PDF文件第10页浏览型号MACH131SP-15VC的Datasheet PDF文件第11页浏览型号MACH131SP-15VC的Datasheet PDF文件第12页浏览型号MACH131SP-15VC的Datasheet PDF文件第14页浏览型号MACH131SP-15VC的Datasheet PDF文件第15页浏览型号MACH131SP-15VC的Datasheet PDF文件第16页浏览型号MACH131SP-15VC的Datasheet PDF文件第17页  
JTAG IN-SYSTEM PROGRAMMING  
Programming devices in-system provides a number of significant benefits including: rapid  
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.  
All MACHxxxSP devices provide in-system programming (ISP) capability through their JTAG ports.  
This capability has been implemented in a manner that insures that the JTAG port remains  
compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through  
which ISP is achieved, customers benefit from a standard, well-defined interface.  
MACHxxxSP devices can be programmed across the commercial temperature and voltage range.  
These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based  
Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes  
the JEDEC file output produced by Vantis’ design implementation software, along with information  
about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/  
VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC.  
Alternatively, Lattice/VantisPRO software can output files in formats understood by common  
automated test equipment. This equipment can then be used to program MACHxxxSP devices  
during the testing of a circuit board. For more information about in-system programming, refer to  
the separate document entitled MACH ISP Manual.  
BUS-FRIENDLY INPUTS AND I/Os  
The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input.  
This double inversion weakly holds the input at its last driven logic state. For the circuit diagram,  
please refer to the Input/Output Equivalent Schematics (page 393) in the General Information  
Section of the Vantis 1999 Data Book.  
PCI COMPLIANT  
The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local  
Bus Specification published by the PCI Special Interest Group. The MACH 1 & 2 families’  
predictable timing ensures compliance with the PCI AC specifications independent of the design.  
POWER-DOWN MODE  
The MACH 1 & 2 families feature a programmable low-power mode in which individual signal  
paths can be programmed for low power. These low-power speed paths will be slower than the  
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while  
the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If  
all of the signals in a PAL block are in low-power mode, then the total power is reduced even  
further.  
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS  
All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system  
designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V,  
while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-to-  
use mixed-voltage design compatibility. For more information, refer to the Technical Note entitled  
Mixed Supply Design with MACH 1 & 2 SP Devices.  
POWER-UP RESET  
All flip-flops power-up to a logic LOW for predictable system initialization. The actual values of  
the outputs of the MACH devices will depend on the configuration of the macrocell. To guarantee  
MACH 1 & 2 Families  
13