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MACH131SP-15VC 参数 Datasheet PDF下载

MACH131SP-15VC图片预览
型号: MACH131SP-15VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能EE CMOS可编程逻辑 [High-Performance EE CMOS Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 48 页 / 1080 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10).  
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate  
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal  
acts as both clock and input to the same device.  
Table 10. Macrocell Clocks  
Device  
Number of Clocks Available  
Device  
MACH211SP  
Number of Clocks Available  
MACH111  
4
2
4
4
4
2
4
4
4
4
MACH111SP  
MACH131  
MACH221  
MACH221SP  
MACH231  
MACH131SP  
MACH211  
MACH231SP  
All flip-flops have asynchronous reset and preset. This is controlled by the common product terms  
that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an  
output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops  
is illustrated in Table 11.  
Table 11. Asynchronous Reset/Preset Operation  
Configuration  
AR  
0
AP  
0
CLK/LE  
Q+  
X
X
X
X
X
0
See Table 9  
0
1
1
Register  
1
0
0
1
1
0
See Table 9  
Illegal  
1
0
0
0
1
0
1
1
Latch  
1
0
0
Illegal  
0
1
0
1
1
1
0
Illegal  
0
1
1
1
I/O Cells  
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left  
permanently enabled for use only as an output, permanently disabled for use as an input, or it can  
be controlled by one of two product terms for bi-directional signals and bus connections. The two  
product terms provided are common to a bank of I/O cells.  
MACH 1 & 2 Families  
11