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MACH131SP-15VC 参数 Datasheet PDF下载

MACH131SP-15VC图片预览
型号: MACH131SP-15VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能EE CMOS可编程逻辑 [High-Performance EE CMOS Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 48 页 / 1080 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Table 3. MACH 1 and 2 Family Package and I/O Options  
Device  
MACH111  
44-pin PLCC  
44-pin TQFP  
68-pin PLCC  
84-pin PLCC  
100-pin TQFP  
100-pin PQFP  
X
X
X
X
MACH111SP  
MACH131  
X
MACH131SP  
MACH211  
X
X
X
X
X
X
MACH211SP  
MACH221  
X
MACH221SP  
MACH231  
X
X
X
MACH231SP  
X
Note:  
1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and  
not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call  
your local Lattice/Vantis sales office or visit our Web site at www.vantis.com for more information.  
®
Lattice/Vantis offers software design support for MACH devices in both the MACHXL and  
DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis  
implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD  
devices. This system is supported under Windows 95, 98 and NT as well as Sun Solaris and HPUX.  
DesignDirect software is designed for use with design entry, simulation and verification software  
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model  
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,  
generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL  
compliant VHDL and SDF simulation netlists for design verification.  
DesignDirect software is also available in product configurations that include VHDL and Verilog  
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model  
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.  
MACH 1 & 2 Families  
3