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MACH131SP-15VC 参数 Datasheet PDF下载

MACH131SP-15VC图片预览
型号: MACH131SP-15VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能EE CMOS可编程逻辑 [High-Performance EE CMOS Programmable Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 48 页 / 1080 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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1
Table 1. MACH 1 and 2 Family Device Features  
Feature  
MACH111 (SP)  
MACH131 (SP)  
MACH211 (SP)  
64  
MACH221 (SP)  
MACH231 (SP)  
128  
Macrocells  
Maximum user I/O pins  
(ns)  
32  
32  
64  
64  
96  
48  
32  
64  
t
5.0  
3.5  
3.5  
182  
5.5  
3.0  
4
7.5 (6.0)  
5.5 (5)  
4.5 (4)  
133 (166)  
7.5  
5.5  
5
6.0 (10)  
5 (6.5)  
PD  
t (ns)  
S
t
(ns)  
4 (6.5)  
CO  
f
(MHz)  
182  
133  
166 (100)  
CNT  
Note:  
1. Values in parentheses ( ) are for the SP version.  
GENERAL DESCRIPTION  
®
The MACH 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex  
Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,  
telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns  
t
and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for  
PD  
users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.  
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Table 2. MACH 1 and 2 Family Speed Grades  
Device  
-5  
-6  
-7  
C, I  
C, I  
C, I  
C, I  
C
-10  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C
-12  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
C, I  
-14  
-15  
C
C
C
C
C
C
C
C
C
C
-18  
MACH111  
C (Note 2)  
C (Note 2)  
C (Note 3)  
C (Note 3)  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MACH111SP  
MACH131  
MACH131SP  
MACH211  
MACH211SP  
MACH221  
C
C
C
C
MACH221SP  
MACH231  
C
C
MACH231SP  
C
Notes:  
1. C = Commercial, I = Industrial  
2. -5 speed grade for MACH111 (SP) = 5.0 ns t  
PD  
3. -5 speed grade for MACH131(SP) = 5.5 ns t  
PD  
The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that  
includes JTAG-compatible in-system programming (ISP). These devices offer five different density-  
I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic  
Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is  
PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed  
timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power  
savings.  
2
MACH 1 & 2 Families