DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
sysI/O Single-Ended DC Electrical Characteristics
V
V
IH
1
1
IL
Input/Output
Standard
V
Max.
V
Min.
I
I
OH
OL
OH
OL
Min. (V) Max. (V)
Min. (V)
Max. (V)
(V)
(V)
(mA)
(mA)
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.4
0.2
0.4
0.2
0.4
V
V
V
V
V
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
CCIO
CCIO
CCIO
CCIO
CCIO
LVCMOS 3.3
LVTTL
-0.3
-0.3
-0.3
0.8
0.8
0.7
2.0
2.0
1.7
3.6
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
3.6
3.6
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
LVCMOS 2.5
0.2
0.4
0.2
0.4
0.2
0.4
0.2
V
V
V
V
V
V
V
0.1
-0.1
-16, -12, -8, -4
-0.1
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
- 0.4 16, 12, 8, 4
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
-0.3
-0.3
-0.3
0.35V
0.65V
3.6
3.6
3.6
CCIO
CCIO
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
0.1
8, 4
0.1
6, 2
0.1
1.5
8
-8, -4
-0.1
0.35V
0.65V
CCIO
CCIO
-6, -2
-0.1
0.35V
0.65V
CC
CC
PCI
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
0.3V
0.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.1V
0.9V
-0.5
CCIO
CCIO
CCIO
CCIO
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
SSTL18 class I
HSTL15 class I
HSTL15 class III
HSTL18 class I
HSTL18 class II
HSTL18 class III
V
- 0.2
V
+ 0.2
0.7
V
- 1.1
- 0.9
- 0.62
- 0.43
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
-8
REF
REF
REF
REF
CCIO
CCIO
V
- 0.2
- 0.18
- 0.18
V
+ 0.2
+ 0.18
+ 0.18
+ 0.125
0.5
0.54
0.35
0.4
V
16
-16
V
V
V
V
V
V
7.6
15.2
6.7
8
-7.6
REF
REF
REF
REF
REF
CCIO
CCIO
-15.2
-6.7
V
- 0.125 V
V
REF
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
V
V
V
V
V
- 0.1
- 0.1
- 0.1
- 0.1
- 0.1
V
V
V
V
V
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
0.4
V
-8
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
0.4
V
V
V
V
24
-8
0.4
9.6
16
-9.6
0.4
-16
0.4
24
-8
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
3-6
LATTICE [ LATTICE SEMICONDUCTOR ]
