DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
LVDS25E
The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in
Figure 3-1 is one possible solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
Bourns
CAT16-LV4F12
VCCIO = 2.5V ( 5%)
RS=165 ohms
( 1%)
+
-
RD = 140 ohms
( 1%)
RD = 100 ohms
( 1%)
VCCIO = 2.5V ( 5%)
RS=165 ohms
( 1%)
Transmission line, Zo = 100 ohm differential
ON-chip
ON-chip
OFF-chip
OFF-chip
Table 3-1. LVDS25E DC Conditions
Parameter
Description
Output high voltage
Typical
1.42
1.08
0.35
1.25
100
Units
V
V
V
V
V
V
V
V
Ω
OH
Output low voltage
OL
Output differential voltage
Output common mode voltage
Back impedance
OD
CM
Z
BACK
3-8
LATTICE [ LATTICE SEMICONDUCTOR ]
