Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V and V
have reached satisfactory levels.
CC
CCAUX
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other V banks are active with valid input logic levels to properly control the output logic states of all the
CCIO
I/O banks that are critical to the application. For more information about controlling the output logic state with valid
input logic levels during power-up in LatticeECP/EC devices, see the list of technical documentation at the end of
this data sheet.
The V and V
supply the power to the FPGA core fabric, whereas the V
supplies power to the I/O buff-
CC
CCAUX
CCIO
ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V supplies should be powered-up before or
CCIO
together with the V and V
supplies.
CC
CCAUX
Supported Standards
The LatticeECP/EC sysI/O buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards.The buffers support the LVTTL, LVCMOS 1.2,
1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable
options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,
BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards
(together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further informa-
tion about utilizing the sysI/O buffer to support a variety of standards please see the the list of technical information
at the end of this data sheet.
Table 2-13. Supported Input Standards
Input Standard
Single Ended Interfaces
LVTTL
LVCMOS332
LVCMOS252
V
(Nom.)
V
1 (Nom.)
CCIO
REF
—
—
—
—
—
—
—
—
—
—
LVCMOS18
1.8
1.5
—
LVCMOS15
LVCMOS122
PCI
3.3
—
HSTL18 Class I, II
HSTL18 Class III
0.9
1.08
0.75
0.9
—
HSTL15 Class I
—
HSTL15 Class III
—
SSTL3 Class I, II
1.5
—
SSTL2 Class I, II
1.25
0.9
—
SSTL18 Class I
—
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL, BLVDS, RSDS
—
—
—
—
—
—
—
—
—
—
—
—
1. When not specified V
can be set anywhere in the valid operating range.
CCIO
2. JTAG inputs do not have a fixed threshold option and always follow V
CCJ.
2-30
LATTICE [ LATTICE SEMICONDUCTOR ]
