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LC4256ZC-75TN100C 参数 Datasheet PDF下载

LC4256ZC-75TN100C图片预览
型号: LC4256ZC-75TN100C
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V / 2.5V / 1.8V在系统可编程超快高密度可编程逻辑器件 [3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 99 页 / 451 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Lattice Semiconductor  
ispMACH 4000V/B/C/Z Family Data Sheet  
LVTTL  
LVCMOS 3.3  
LVCMOS 2.5  
LVCMOS 1.8  
• 3.3V PCI Compatible  
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down  
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both  
hardware and software is such that when the device is erased or if the user does not specify, the input structure is  
configured to be a Pull-up Resistor.  
Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be  
individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set-  
ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflec-  
tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the  
fast slew rate can be used to achieve the highest speed.  
Global OE Generation  
Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a  
2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or  
GOE pins. Each signal that drives the bus can optionally be inverted.  
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a  
256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10  
show a graphical representation of the global OE generation.  
Figure 9. Global OE Generation for All Devices Except ispMACH 4032  
Internal Global OE  
Global OE  
PT Bus  
(4 lines)  
4-Bit  
Global OE Bus  
Shared PTOE  
(Block 0)  
Shared PTOE  
(Block n)  
Global  
Fuses  
GOE (0:3)  
to I/O cells  
Fuse connection  
Hard wired  
12