Specifications
ispLSI 2064E
ispLSI 2064E Timing Model
I/O Cell
GRP
Feedback
GLB
ORP
I/O Cell
Ded. In
#21
I/O Delay
#20
GRP
#22
Comb 4 PT Bypass #23
Reg 4 PT Bypass
#24
20 PT
XOR Delays
#25, 26, 27
D
RST
GLB Reg Bypass
#28
GLB Reg
Delay
Q
#29, 30,
31, 32
ORP Bypass
#37
ORP
Delay
#36
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
Reset
#45
Control RE
PTs
OE
#33, 34, CK
35
Y0,1,2
GOE 0,1
#43, 44
#42
#40, 41
0491/2064
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
t
su
=
=
=
3.1ns =
=
=
=
3.4ns =
=
=
=
7.9ns =
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 2.9) + (1.2) - (0.5 + 0.6 + 1.0)
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (2.3) - (0.5 + 0.6 + 2.9)
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
Table 2- 0042A-2064e
t
h
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2064E-200L.
7
LATTICE [ LATTICE SEMICONDUCTOR ]
